Thanks for the post on Intel's patent.
starting with
"A chip comprising:
a memory array including a plurality of rows corresponding to neurons in a spiking neural network (SNN);
a row decoder coupled to the memory array, the row decoder to activate a row in the memory array in response to a pre-synaptic spike in a neuron associated with the row;
a sense amplifier coupled to the memory array, the sense amplifier to determine post-synaptic information corresponding to the activated row; and
a processor including logic coupled to the sense amplifier
"
While it relates to Loihi in that it identifies processing between synapses, i think it is also marking out the ground for eventual use of memristor technology for compute in memory as is applicable to WBT long term goals,
It also suggests that there may be use cases of interest for such processing in SNN.
Looking at the instruction codes in other documentation on Loihi 2, the sort of processing is minimal, barely and/or and test <=>.
I don't see it as a threat to BRN, if there is any logic processing to be done on a recognized SNN change of state, it can be done as required in the ARM PU rather than have a whole memory array with chip space devoted to such functions per neuron/synapse.
Maybe the BRN brains trust should look over the patent and think about where they could put in some computation.
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