Automotive SoCs for ADAS [IMG] Renesas has announced the...

Automotive SoCs for ADAS

Renesas has announced the development of processor technologies for automotive systems-on-chip (SoCs) used in applications such as advanced driver assistance systems (ADAS) and autonomous driving (AD) systems.


The company said that these technologies were intended to optimise both performance and power efficiency while supporting a high level of functional safety.

Renesas said that its development includes: a convolutional neural network (CNN) hardware accelerator core that delivers a combination of deep learning performance of 60.4 trillion operations per second (TOPS) and a power efficiency of 13.8 TOPS/W; safety mechanisms for fast detection of and response to random hardware failures - making it possible to create a highly power efficient detection mechanism with a high failure detection rate; and a mechanism that allows software tasks with different safety levels to operate in parallel on the SoC without interfering with each other, thereby bolstering functional safety for ASIL D control.

Applications such as next-generation ADAS and AD systems require deep learning performance of 60 TOPS or even 120 TOPS alongside power efficiency.

In addition, since signal processing from object identification to the issuing of control instructions constitutes the bulk of the processing load in autonomous systems, achieving the functional safety equivalent to ASIL D – the strictest safety level defined in the ISO 26262 automotive safety standard – is a pressing issue.

Renesas has developed a number of new technologies to meet these needs, including a hardware accelerator that delivers outstanding CNN processing performance with superior power efficiency. These technologies are listed below:

• A CNN hardware accelerator with superior power efficiency.
• Safety mechanisms for ASIL D systems capable of self-diagnosis.
• A CNN hardware accelerator core with improved deep learning performance.
• Safety mechanisms for fast detection of and response to random hardware failures occurring in the SoC overall.

Author
Neil Tyler