"My reasoning is that I can’t predict if/when a potential suitor might decide that the testing has gone far enough for a substantial offer to be tabled."
Hey brother, I'm no techo but I'll have a crack...
But first let me capture another quote regards platform iterations.. Cause it is possible we may be done..
"And then, in last week’s highly-anticipated update (September 20):“4DS…has analysed the first lot of 300mm wafers from imec…
This was the first of a number of planned iterations.”
It was and this was the company statement on Feb 1... Calling out immediately progressing to next fab run with dense memory arrays and control logic.. And which is expected to pave the way to pursue the strategic objective of fabricating wafers & chips that are fully functioning megabit memories.
Depends on your take but that can be read as after this lot we will have a defined process for volume production of FF megabit memory units.
TMT analytics Feb 2019...
Note last paragraph: However, the company should now be able to turn around any upcoming test batches much quicker than before, i.e. 3 months instead of the earlier 6 months, which will speed up the development process as a whole.
Once the iterative process is complete, which could be as early as the end of Q2,
4DS will be ready to mount its array on imec’s platform. This platform is
imec’s standard carrier for memory arrays and the integration is straightforward and very low risk.Only once the iterations have concluded (i.e no more tweaking design) then 4DS will be ready to mount its array con logic controls on IMEC's standard memory array integration platform... The outcome of which is straightforward and therefore "
Very Low Risk"I don't believe, based on interpretation of the process and inline with the official company statement, that there will be another run... I believe they are going through final motions now and this is the confirmation run, we've done it...
As for endurance, retention etc... Not a problem.. when they say adequate for SCM here is the current std.
As NVMs, all of these technologies share reliability considerations with flash memory, in addition to the considerations that apply to all integrated circuits.
Of particular importance are data retention and endurance. Neither of these is an issue for volatile memories like DRAM and SRAM. Ironically,
they’re not an issue for DRAM because its data retention is so short that refresh circuitry is a basic DRAM requirement, making data loss a non-issue as long as power is maintained. In general, refresh is considered undesirable (although possible) in these new NVM technologies.
"Cycling endurance: The number of times a memory cell can be switched from a LRS (a value of 1) to a HRS (value of 0) and back is called cycling endurance. 4DS’ Class 1 performance shares, expiring on 31 December 2018, are based on the company achieving a minimum number of switching cycles (from 0 to 1 and back)."
"Data retention: The amount of time a memory cell can stay in a LRS or HRS, and thus represent a value of 1 or 0, is an important metric for memory manufacturers. Data retention will typically improve if higher energy levels are used to switch the cell. However, this may result in the cell degrading faster. So a balance between the two needs to be found, again depending on the specific end application."
Data retention is linked to the other basic NVM spec,
endurance. Each time an NVM is programmed, some slight damage may occur. In flash, that would come as a result of electrons becoming embedded in the dielectric separating the floating gate from the rest of the circuit. Defects also may occur that can hasten the leakage of electrons off of the floating gate.
Endurance is the number of times a memory can be programmed before the data retention falls below spec.In theory, it’s possible to program a given device beyond its endurance, and it’s likely to continue to operate – but with shorter data-retention. Some devices may, however, count programming cycles and block programming beyond the limit.
For many years, 10,000 cycles was the bar that flash memories were expected to reach. Nowadays, more and more memories are specifying 100,000 cycles.
Each NVM technology — and the new ones are no exception — has a means of data gradually leaking away.
So data retention becomes a guarantee that, for some period of time, the memory will keep its contents. After that, it still may keep its contents for longer, but there’s no guarantee.
Ten years has been a typical spec for flash, although automotive applications are pushing that requirement out, given the long lifetimes of cars.
SSD Retention Std..JEDEC Solid State Technology Association, an independent semiconductor engineering trade organization and standardization body, defines two specifications applicable to SSD endurance. The JEDEC specification for commercial flash SSD devices call for a client class SSD device to maintain a bit error rate (BER) of 10-15 or less, and retain data for minimum of one year at 30°C. The JEDEC spec also defines the data retention at elevated temperatures, but the retention time is quite alarming. Per JESD218, a client class SSD must maintain its data integrity at the defined BER for only 500 hours at 52°C (less than 21 days) or 96 hours at 66°C (only four days).
Feb 2019.. results from Additional Wafer Lot & Lot one... Endurance analysis of the wafer with the best characteristics in this batch (wafer D17) showed that the number of times 4DS’ Interface Switching ReRAM technology can be switched runs
“into the millions of cycles”. June 20.. Now 4DS is in the 10's of millions of cycles far exceeding Flash & other SSD's and validated as more than adequate
As for retention... it is dependent on workload, cycles and temperature.. AARON FRANKSenior Product Manager, Intel SBC & Graphics
Flash SSD devices which are specifically designed for high-temperature operation must support reliable data retention at operational temperatures exceeding 85°C, and at storage temperatures often quoted up to 125°C. Rarely however, will a flash vendor guarantee data retention at these high temperatures because the length of storage time at extreme temperatures is frighteningly low. Take, for example, the chart in Figure 1 (above) where the device is rated for 10-year data retention at 40°C.
Interpreting the graph for a 100,000 P/E cycled cell at a storage temperature of 115°C returns an unacceptably low data retention time of about one day. Luckily, the same uncycled cell stored at 115°C has a retention time close to a year.4DS has a technology which is all but proven to be as faster if not faster than DRAM with p/e cycles running in to the 10's of millions to possibly billions at 10'9x and beyond.. Therefore we can calculate overall drive endurance as measured against baseline parameters already. !!
Ref below
https://www.ni.com/en-au/support/documentation/supplemental/12/understanding-life-expectancy-of-flash-storage.html#section-99108663
Calculating Drive Endurance Drive Endurance can be determined once the Flash Cell Endurance, Storage Time Factor, Amplification factor for Temperature, and Write Amplification Factors are known. Recall the drive endurance formula:
Example 1 64 GB SLC SSD with a non-operating (storage) temperature of 40°C with streaming data logging (sequential writes) with 1 year of desired data retention. SLC Flash Cell Endurance is 100,000 P/E cycles, STF and AT are both 1 (since we’re at baseline 1 year at 40C), and the WAF is 1 for the "100% Sequential" model. Total Bytes Written before end of life = 64 GB x 100,000 Drive Writes = 6400 TB
Example 3 128GB eMLC SSD with a non-operating (storage) temperature of 55°C with an unknown write profile with 24 months of desired data retention. eMLC Flash Cell Endurance is 20,000 P/E cycles, STF is 2 (24/12 months), AT is 6.4 for 55°C storage temperature, and the WAF is 4 using the “Rule of Thumb” model.
Total Bytes Written before end of life = 128 GB x 390 Drive Writes = 50 TB
Based on a std formular and using worse case scenario given to weight storage, work amplification & temperature factors we arrive at the following figures for 10'000'000 million cycles so that the worst case scenario is still greater than the example given in scenario 3 for a 128GB MLC SSD drive..
Reram has previously been shown to equal DRAM at 60-100 Memory Cell size (F2)
And if anyone is concerned about scaling up to Gigabits.. I wouldn't worry too much... Seems this lot (SanDisk) know a thing or two already.. And I believe are associated with WDC & HGST who started with 4DS around 2014!!!!
hahaha Stick a fork in her Jerry, this one is done.. End of this run once we have paved the way is my guess.... let's see?
8tey