10/08/2020 - CompanyUpdate
As such, the Company now proposes to start fabrication of two sets of wafers this quarter on imec production equipment. imec will manufacture one lot of twenty-three (23) Non-Platform Wafers (Second Non-Platform Lot) and one lot of twelve (12) Platform Wafers (Second Platform Lot).
The original plan to develop 12 Platform wafers (Second Platform) changes to 18 Platform wafers (Second Platform) with a major shift in scope.
Second Non-Platform Lot
The Company is defining the process conditions for each of these 23 wafers in collaboration with its partners. These wafers are less complex, faster to fabricate, and easier to test than Platform Wafers, yet can provide valuable input on which process conditions exhibit the biggest improvements in speed, endurance and retention.
Second Platform Lot
Testing process integration in incremental steps is important to define refinements which are needed to reach the Company’s goal of manufacturing a fully functional megabit chip with Storage Class Memory characteristics.
The objective of the Initial Platform Lot was to test the integration of dense memory arrays without the complexity of transistors. 4DS validated the integration process, and recent meetings and discussions have identified process steps and conditions that are designed to benefit the fabrication of the Second Platform Lot.
Significantly, the outcome of development discussions is that the Second Platform Lot will be fabricated to contain dense memory arrays with transistors that are able to select memory cells.
This is a major strategic decision to better ensure success in 2021 when, based on the results of this Second Platform Lot, 4DS and its partners will potentially progress to fabricate wafers with all the control logic necessary to read and write selected bits and bytes, and therefore be able to operate as a fully functional megabit memory.
Both lots of wafers will be fabricated with variations of the process conditions from the best wafer in the Additional Wafers Lot, which had exhibited the biggest improvements in speed and endurance in the Company’s history.
10/12/2020 - CompanyUpdate
”In conjunction with imec, 4DS has identified some further refinements to process conditions for the Second Platform Lot wafers, which are expectedtomitigaterisks at various stages in the fabrication process”.
Here IMEC with 4DS are aiming to nail the Second Platform Lot by discretely announcing changes to the original scope.
01/02/2021 - POSITIVE RESULTS FROM SECOND NON-PLATFORM LOT
“ThelearningsfromtheSecondNon-PlatformLot have been incorporated into the process split conditions for the Second Platform Lot of 300mm wafers.
The Second Platform Lot is using imec’s memory platform, and contains dense memory arrays with the control logic necessary to read and write selected bits and bytes”.
4DS declares the major shift in the scope of works, which to our advantage accelerates the development process. This would explain why the Second Platform Lot was tactically delayed.
“The results from the analysis of the SecondPlatformLotareexpectedtopavethewayfor4DSanditspartnerstopursuetheirstrategicobjectiveoffabricatingwaferswithchipsthatoperateasfullyfunctionalmegabitmemories, and which have been produced using state of the art industry fab equipment. If successful, thismaybring4DSclosertoits2021objectivestoachieveapotentialcorporatetransaction”.
4DS is expecting successful run with the Second Platform Lot, leading it to achieve the corporate transaction and/or megabit chip.
21/06/2021 - 4DSRECEIVESIMECWAFERS
Second Platform Lot
As previously advised during the quarter imec were finalising the production of the Second Platform Lot and 4DS is pleased to advise eighteen (18) wafers have now been received at its Fremont facilities.
The additional 6 wafers from the originally planned 12 are likely to be the result of changing the scope of works. Added complexity to the development process would likely mean more wafers to sufficiently provide meaningful data.
Third Non-Platform Lot
The Company also took the opportunity to utilise spare capacity on imec state-of-the-art commercial production equipment to manufacture a Third Non-Platform Lot comprising of twenty-three (23) wafers. This decision was undertaken to ensure the Company continues to build an extensive data set around the process parameters for its Interface Switching ReRAM technology.
Like theSecond Non-Platform Lot, the Third Non-Platform Lot also consisted of 23 wafers. This is likely to further validate the positive data collected from the Second Non-Platform lot. Probably something that was needed to unequivocally affirm key memory characteristics (speed at near DRAM, endurance and retention). This piece of work according to previous announcements was not originally planned, so having this done now on the back of positive results means we are well advanced in Fab qualifying a commercial production process for our unique market disruptive “Non-Filament Interface Switching ReRAM”.
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