4DS - Anything but Charting, page-18260

Last Technical Update interpretation ..................................



Although there were seemingly important technical progress at the Cell level (Non-PlatformLot), some parts of the announcement were rather disappointing.
Even frightful for some that entered recently in this investment.

"The Company has also for the first time demonstrated memory cell switching using an access device which is a critical step for producing a functional megabit memory array."

This means that still have to make some progress to have the cells funtionning in an array.
A number of shareholders thought that the technology was much more advanced than that.

It is like a company which had promised the best car ever (the # Ferrari ) and boasted because they managed to have some gas reaching one cylender.
When shareholders were waiting for the car to be ready to run and thought that they have to wait for the roads to be ready, they discovered that the revolutionnary engine of the car was far from working.
And that meant one or two years of developpement before pay day.
(Initial Platform Lot = 10 months between decision and results analysis ; Second Platform lot = 12 months between decision and results analysis)

And that after shareholders were promised something not exactly like a megabit memory but close to it (being able to select bits and bites).

Very very disappointing.


But other parts of the announcement gave a different picture. Not necessarily more optimistic about the timeline, but different...
As in a "different" type of investment.

4DS has for the first time demonstrated fabrication of fully crystalline Pr1-xCaxMnO3 (“PCMO”)at temperatures compatible with the advanced processes run in today’s leading-edge high-volume memory DRAM and NAND factories;

One hour of research bring the following informations :

https://www.osti.gov/servlets/purl/1426910

A CMOS Compatible, Forming Free TaOxReRAMA.J. Lohn, J.E. Stevens, P.R. Mickel, D.R. Hughart, M.J. MarinellaSandia National Laboratories, Albuquerque, New Mexico 87185, USAEmail: [email protected], Phone (505) 844-7848Resistive random access memory (ReRAM) has become a promising candidate for next-generation high-performance non-volatile memory that operates by electrically tuning resistance states via modulating vacancy concentrations. We demonstrate a wafer-scale process for resistive switching in tantalum oxide that is completely CMOS compatible. The resulting devices are forming-free and with greater than 1x105cycle endurance.IntroductionResistive random access memories (ReRAM), also referred to as memristors, have emerged in the past several years as a leading emerging nonvolatile memory device due to excellent scalability[1]and stackability[2], low energy[3], and high endurance[4]. Furthermore, the analog properties of this device are a potential enabler of neuromorphic computing[5]. Of particular interest are the class of ReRAM based on based on the mechanism named valence change memory (VCM) and fabricated from transition metal oxides (TMOs) such as TaOx, HfOx, and TiO2[6]. Switching in of VCM ReRAM is the subject of continued research, but is thought to occur as a result of oxygen vacancy motion in a small (50-200 nm) channel created inthe TMO region of the device [7]. This particular class of ReRAM has achieved record endurance (1012cycles) [4], sub-nanosecond switching speeds [3], and demonstrated operation in 10x10 nm devices [1].
Note that all of these metrics are for research devices, not integrated with a CMOS process.
In fact, two of the significant hurdles to overcome with ReRAM technology are integrating high performance ReRAM devices with a CMOS back end of line (BEOL) processes[8,9]and eliminating the high voltage electroforming step[10]. This work reports on initial results from the wafer-scale integration of a TiN/Ta/TaOx/TiN ReRAM stack using a process compatible with CMOS. These initial results demonstrate that a CMOS integrated process which does not require a high voltage forming step and exhibits performance on par with integrated flash memory.

From this paper and many others, it seems that integrating 4DS ReRam with a CMOS process (the Imec platform) is not as easy as it was announced.

https://www.ims.fraunhofer.de/en/Business_Units_and_Core_Competencies/Devices-and-Technologies/Technologies/Customer-Specific-CMOS-Processes.html

But other companies managed to have megabit ReRam memories with simpler connexion with the CMOS end of line platform, but with coarse connections that can be used for test purpose, but that cannot be used in an industrial process.

Imo, in an industrial process, the ReRam layers are created on top of CMOS layers and the CMOS has to connect with the ReRam Layers above.

All this is subject to rectifications by more informed posters.

But from what is avaible after a quick research, there are two problems : The temperature with high voltage used for electroforming and pressure.
We know that non-filamentary ReRam doesn't need electroforming. That is typical of filamentary ReRam.
So the 4DS ReRam might no encounter this problem when the different layers are deposited on the wafer.
But they might have encountered other problems when trying full crystallisation of the PCMO layer.

It is interesting to note that they mentionned temperature for the first time.

4DS has for the first time demonstrated fabrication of fully crystalline Pr1-xCaxMnO3 (“PCMO”)at temperatures compatible with the advanced processes run in today’s leading-edge high-volume memory DRAM and NAND factories;

Other interesting point is the fully crystalline PCMO.

A fully crystalline layer are usualy achieved at atomical levels.
What the technical litterature says is that temperature and pressure are needed to reach crystallisation, depending on the composition of the reistance layer.
It is also conceivable that this very thin (atomic level) fully crystalline PCMO needs a special surface under it. Surface issue ?

Crystalline PCMO has always be part of the 4DS project. It is mentionned in this 2014 document.

https://www.vlsiresearch.com/metal-oxide-hetero-junction-operation-nonvolatile-memory-mohjo-PFEL1SE1UU8KZDQ#page1



The question is : why does it comes so late in the Imec experiment ?


INTERPRETATION

One interpretation could be that their initial strategy never was to reach full integration with CMOS.
Just demonstrate the Cells perfomance with coarse connections with the Imec memory platform for test and demonstration purpose.
The buyer will have to developp its own platform anyway. WD couldn't sell their product fitted with an Imec part.

Hence the JD comment about how the connection with the Imec platform being the easiest part of the job.

It could be that this strategy changed and now they seem to want full integration to offer their clients a totaly turn key product (or a complete recipe for an end product).

- Either they met with technical hurdles trying to make cells array working with the Imec platform ;
- Or they decided to go for the full prize and use a fully crystalline PCMO knowing that it will pose integration problems or delays.

Their are two facts that could that point to the later (Ie : Decision to reach the full potential of the tech, delays (and shareholders) be damned) :
- DM obvious discontentent and his decision to sell parts of his shares
- JD leaving the board and selling arround 8 or 9 millions shares.

__________

It should be noted here that JD only sold the necessary amount to reach free carry.
- JD holding : 53 436 004 shares or 54 686 004 shares if he managed to exercised his 1 250 000 options (all vested) before his departure.
- JD holding as per August 2021 annual report : 45 286 004 shares
- Amount sold = 8 150 000 shares without his options being exercised - or - 9 400 000 shares if his options were ercised and sold.
- Amount collected arround 1 million or 1,15 million USD wich wich could be rounded to 1 million USD after taxes (if sold at 0,17)

= the amount invested at the beginning of the story.

It is only reasonnable to get back your initial investment when you don't have your say in the strategy of the company.

__________


There is another intriguing note in the announcement.

This significant performance improvement also means that full characterization (speed, endurance, retention) of memory cells with this fully crystalline PCMO material requires memory cells operating in a memory array where currents are controlled and limited by access devices.

This is a weird comment.

We all know that characterisation imply that the cells work in an array.
This is the point of making a megabit chip.

Interpretation could be :
- They already made memory cells that funtionned in a memory array, but they have to try it again because they now use a fully crystalline PCMO material. => change at the cell level have induced more delay for the megabit chip.
- They are not talking to shareholders (or no only) but to the industry researchers and they have to tell things that they already told to shareholders.

What seems clear today is that they are still making progress at the cell level.
Imo, we can even say that all their effort were focussed on the cell.

That's why they delayed the second platform lot that was initialy scheduled for december 2020. In december 2020 they decided to integrate what they found in the second Non-Platform lot in the Platform in the making.
(Finally, the 2nd platform lot took 12 month to make, from decision to result analysis).

And with this new progress at the cell level they need one more iteration to integrate a crystalline PCMO with a CMOS platform.


CONCLUSION

- The new board wants to reach the full potential of the tech ;

- Each progress at the cell level means a new try at the megabit array level ;

- They don't realy care about delays ;

- They are talking to the industry through shareholders announcements.

“4DS Memory has made significant and industry recognisable progress..."

- The value proposition has changed : they are no more looking for a takeover (even if it probably remains the most probable outcome), but for commercialising the technology ;

- Taking this route could explain JD leaving and DM selling.

- The value is in the technology. Reading of recent technical and scientific papers clarifies that what they achieved at the cell level is what everybody is looking for ;
(This is at the very edge of industrial feasability. This has a financial value, but not for even techno savy investors. It has value for those working in top research centers or companies labs. There are technical thresholds that are only visible by scientists.)

- Unless 4DS could be included in recent consolidation movements between WDC and Kioxia, Shareholders should expect progressive rerate with a two years horizon ;
It could come faster if 4DS becomes more visible.

- Extreme secrecy and clear disdain for shareholders still point to probable surprises.


All subject to better informed members rectification.
No financial advice.