[ATTACH] Integration of dense memory arrays onto platform :...

Integration of dense memory arrays onto platform : Validated

Note it appears these platform lots were sequential, each adding to the next.

Ie: 1st platform lot had no transistors but validated the integration process

Note the goal is a chip with " storage class characteristics "

2nd platform lot glitched courtesy of the mask however they scaled to the lowest geometries. Fair trade off if you ask me. The endurance degradation on accounts here seems a non issue.

Our characteristics appear pretty close to storage class which should be good enough for commercialisation or a transaction remembering this will be multi generational with tens or hundreds of future iterations down the track should this occur. Im also thinking the cto went now we are pcmo'ing our way forward. No biggie.

And remember the enticing power saving clinchers too.

Waiting for a CR could be an each way bet.

An updated top 20 will be very interesting

Onya those who held on.