@hashtagyoloHey Unc, & along with all & sundry... Happy New...

@hashtagyolo

Hey Unc, & along with all & sundry... Happy New Year.. @patience I owe you a Gorilla... Although in all fairness we pulled back 100% from the lows, which if the ann had of been better crisis managed perhaps may have meant we held 13c & not 4.5.. 100% increase from which would have been 26c but that's a long bow to draw I know B**ger

Anyway, back to my main point Good little article ref this one Hash.. Gracias

https://www-forbes-com.cdn.ampproject.org/c/s/www.forbes.com/sites/tomcoughlin/2021/12/29/digital-storage-projections-for-2022-part-2/amp/

Bit of a Rabbit Hole as they all are but it puts forward a plausible scenario & timeline.
Plus gives enough insight into why the focus on NAND Flash has waned and DRAM has elevated when you delve into it, along with who the major players/drivers are and the author has cred within the industry so I'm happy to take it at face value.


So what's he say?

NAND flash memory has become the dominant primary storage in data centers and enterprises and is the storage used in consumer devices such as smart phones and tablets and now dominates as storage in PCs. Active data now lives on SSDs with colder data kept on HDDs or magnetic tape,

SSD companies are trying to put pressure on HDDs for secondary storage. They are primarily doing this with very high layer count NAND flash as well as quad-level cell (QLC) flash that stored 4-bits per flash memory cell (Kioxia and WDC have talked about 5-bit per cell NAND flash, although no products are in production).

Micron was the first to announce 176-layer NAND flash in 2020 followed by SK hynix, late in 2020. WDC and Kioxia announced a 162-layer NAND flash in February 2021. Samsung released its 7th generation V-NAND in a consumer SSD in 2021. The Samsung 7th generation V-NAND has 176 layers without increasing the modules height compared to its 6th generation product with 128-layers, with a 35% smaller cell volume. Samsung is using a single stack NAND layer etching technology that allows a smaller chip area and height. Samsung says it can go up to 256-layer single stack NAND and announced that its Generation 8 V-NAND will be over 200 layers. Samsung has projected that 3D NAND could evolve to over 1,000 layers (SK hynix has said over 600 layers).

Basically that Nand Flash is going to keep stacking vey nicely thankyou and ergo the need for a replacement isn't as important as it once was.. However maintaining market share is... Anyone remember this?





WDC were indeed working towards a 5bit per cell configuration as highlighted by this man below and in fact he called out a major phone manufacturer (Samsung?) as being a possible early adopter of the WDC new technologies in his August telecon with Asian Investors.. But seeing as how V-Nand is proprietry to Samsung and doing quite nicely thankyou, I wonder if he was talking about Nand, or other products, architectures etc.. ?


Either way the Flash Roadmap is set and it would be a brave move to push a new product onto the market which then essentially competes with your current product, if you can produce at the cost per bit? Which considering the increases in capacity you may well not just yet..

Samsung are now saying their gen 8 V-Nand could stack to over 200 layers and 3D Nand possibly 1000.. And whilst Samsung may have been the early adopter, the CFO spoke of, they are also a competitor in the FLASH space.. Although they do have a DRAM interest & WDC had no roadmap for manufacturing DRAM as the article points out when the merge was first floated..


So it is my gut feel that at around the same time WDC announced they were reimaging the HDD & boosting SSD's that they decided to sit on the tech for now and concentrate on NAND..

However, the connection to Global Foundries via the WDC board appointment means they may well have tipped their hat to Samsung to position for the DRAM end of things because GF manufacture for Qualcomm who supplies Samsung






And as we know Samsung leads DRAM.... Which as we know is facing headwinds.. So what is Samsung now loking at according to Coughlin 3D DRAM Stacking..

DRAM replacements?
For years, meanwhile, the industry has been developing several next-generation memory types that could replace DRAM and flash.

Today, vendors are shipping phase-change memory (PCM), ReRAM and STT-MRAM. Other memory technologies are in R&D.

The next-generation memories are fast, nonvolatile and provide unlimited endurance. But these new memories also rely on exotic materials and complicated switching mechanisms, so they have taken longer to develop. Plus, the new memory types are more expensive.

Each new memory type is different. PCM stores information in the amorphous and crystalline phases. STT-MRAM uses the magnetism of electron spin. ReRAM works by changing the resistance of materials.

Today, PCM and STT-MRAM devices are used in select parts of SSDs. They are used in place of DRAM in some but all not parts of the system. So, it’s safe to say they haven’t exactly replaced DRAM.

“At this time, we cannot see any next-gen type of memory that can directly replace DRAM,” said David Hideo Uriu, product marketing director at UMC. “We do see an SRAM replacement through the use of MRAM. But for the goal of a persistent DRAM replacement, we can only see a ‘hybrid cached’ DRAM/MRAM component.”

STT-MRAM itself is making progress. “MRAM technology will continue to improve and move closer to the goal of persistent memory. MRAM is the closest technology to match the speed and performance of DRAM,” Uriu said. “Given the near DRAM speed of reading data, some applications may be able to use it as a replacement for some DRAM. Again, in its ‘hybrid’ form, DRAM will be used to cache the MRAM storage areas and improve performance to be a DRAM replacement in some applications.”

Conclusion
To be sure, the next-generation memory types are promising. But these products are still in the early days.

Until then, DRAM is alive and well, and it likely will stick around — at least for the foreseeable future. But exactly how long remains a big unknown.

AI memory
In the works for years, ReRAM once was touted as a NAND replacement. But NAND has scaled farther than previously thought, causing many to re-position ReRAM.

Today, some are working on embedded ReRAM. Others are developing standalone ReRAM for niche-oriented applications. Longer term, ReRAM is expanding its horizons. It’s targeted for AI apps, a DRAM replacement, or both.

while simultaneously reducing power consumption by 70%.

But whilst there are benefits to be gained there is still an issue with PIM based systems.. Namely that it couldn't escape the bottleneck issue.. Until now that is..

Limitations of PIM: 1) Although RADAR provides significantacceleration, it encounters an Amdahl’s Law bottleneck with thethird stage, gapped extension, of the BLASTN algorithm. Althoughthe first two stages, which compose 99.8% of the algorithm runtime,can be accelerated by 5114 times, the remaining stage cannot besolved with the PIM hardware, and the total acceleration ratio isreduced by an order of magnitude to about 456x. 2) To supportBLASTN acceleration, other support hardware, including buffersand computation logic, must be added to the ReRAM memory arrays.This extra hardware introduces more than a 25% area overhead evenbefore considering efficiency loss from array alignment and poormemory transistor performance. 3) The internal memory bus andexternal interfaces are further communication bottlenecks. Each4MB unit (with 64 ReRAM arrays) can concurrently produce over6KB of 46-bit word match messages, which is over 18KB with thenative 128-bit memory word length. For example, in a 32 GB RADARsystem with 8K of these units, 155MB may be produced during eachquery, requiring more than 1.8 TB/s bandwidth.


Monolithic 3D RERAM... Both Stanford & AMD have been all over this for a few years now...

NETWORK-ON-CHIP IN MONOLITHIC 3D © 2019 Advanced MicroDevices

ACKNOWLEDGMENTS
AMD, the AMD Arrow logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names usedin this publication are for identification purposes only and may betrademarks of their respective companies. © 2019 Advanced MicroDevices, Inc. All rights reserved

© 2019 Copyright held by the owner/author(s). Publication rights licensed to ACM.
ACM ISBN 978-1-4503-6725-7/19/06. . .
https://doi.org/10.1145/3316781.332347
The significance of which isn't fully appreciated until you realise Intel are no longer a premier development partner of WDC... Only AMD is now as per the website. Which may well side line Intel & Micron ??

So the need for an axis of innovation, being heterogeneous Integration & Miniaturization, may well have been met already by none other than AMD, the team at Stanford & Samsung who have claimed to have new dram architectures ready..

They lead the pack with their OLED phones, have their own capacity to manufacture DRAM plus agreements in place with GF, Qualcomm & AMD to supply components for the new technologies planned.. Throw in a possible gentlemen's agreement with WDC to agree to play fair in the Flash space in return for bit stacking advice (the reality of which is pure speculation only based on a personal opinion) & things are starting to take shape again we could postulate?

CONCLUSION
Monolithic 3D integration can improve circuit density and reduce interconnect power, but system-level architectures must be optimized to improve power efficiency. This work proposes an M3D targeted NoC architecture to provide efficient communication for dense M3D systems with reduced interconnect utilization. This work also analyzes the heterogeneous M3D integration of NVM for storage and PIM with improved area and performance efficiency.




Ref IEEE/IEDM talks.

Abrash mentioned the possible use of spintronics, 2D materials, carbon nano tubes (CNRTs), functional interconnects, flexible and meta-materials) to enable higher system performance a lower unit power density and smaller physical volume to enable these wearable future devices.

He also mentioned the need to develop new architectures and domain-oriented accelerations to support machine learning (ML) but also for particular applications such as avatar tracking and reconstruction, audio, eye tracking and electromyography with wearable sensors on the users arms. Algorithmic optimization will be needed for model compression, low precision computing and platform-aware design optimization.

Current AR/VR computing systems consumer the most power in data transfers and memory access. On-sensor computing and memory-centric computing approaches such as compute-in-memory will be needed to tackle these bottlenecks. In addition, tighter physical coupling of logic with memories, logic with sensors and displays can help reduce data movement. He also mentioned the importance of using embedded non-volatile memories like spin transfor torque magnetic random-access memories (STT-MRAM) will be important in achieving power and area optimization since these memories have higher density that SRAM and are non-volatile, allowing more lower power states.

He talked about advances in image sensors that include the use of a hybrid memory hierarchy (including SRAM and eNVM, such as MRAM) in on-sensor ML computation architecture to allow for higher density and lower power. 3DIC technologies, such as three-layer stacking, through silicon vias (TSVs) and wafer-level hybrid bonding, will enable this heterogeneous monolithic integration. The figure below shows a multi-camera AR/VR distributed multi-camera computing system with various features, including the use of the hybrid memory systems. The figure also indicates the energy and communication requirements for the various computing/communication paths.