For what it's worth this is where I think they are heading in part at least... DRAM is about to get owned by the monkey on its back. :-) 8tey

Noting this mob wouldn't have had 4DS speed when they ran this sim..

"We apply our monolithic design ideas to a many-core CPU by integrating 3D ReRAM over each core's LLC slice. We find that co-design of the LLC and ReRAM saves 27% of the total LLC–main memory area at the expense of slight increases in delay and energy. The streamlined LLC/main memory interface saves an additional 12% in area."

"Our simulation results show monolithic integration of CPU and main memory improves performance by 5.3×5.3× and 1.7×1.7× over HBM2 DRAM for several graph and streaming kernels, respectively."

Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache

CANDACEWALDEN,

DEVESHSINGH,

MEENATCHIJAGASIVAMANI,

SHANGLI,and

LUYIKANG,

University of Maryland, College Park

MEHDIASNAASHARIand

SYLVAINDUBOIS,

Crossbar Inc.

BRUCEJACOBand

DONALDYEUNG,

University of Maryland, College Park

ACM Trans. Archit. Code Optim., Vol. 18, No. 4, Article 48, Publication date: July 2021.
DOI:https://doi.org/10.1145/3462632

Many emerging non-volatile memories are compatible with CMOS logic, potentially enabling their integration into a CPU's die. This article investigates such monolithically integrated CPU–main memory chips. We exploit non-volatile memories employing 3D crosspoint subarrays, such as resistive RAM (ReRAM), and integrate them over the CPU's last-level cache (LLC). The regular structure of cache arrays enables co-design of the LLC and ReRAM main memory for area efficiency. We also develop a streamlined LLC/main memory interface that employs a single shared internal interconnect for both the cache and main memory arrays, and uses a unified controller to service both LLC and main memory requests.

We apply our monolithic design ideas to a many-core CPU by integrating 3D ReRAM over each core's LLC slice. We find that co-design of the LLC and ReRAM saves 27% of the total LLC–main memory area at the expense of slight increases in delay and energy. The streamlined LLC/main memory interface saves an additional 12% in area. Our simulation results show monolithic integration of CPU and main memory improves performance by$5.3\times$and$1.7\times$over HBM2 DRAM for several graph and streaming kernels, respectively. It also reduces the memory system's energy by$6.0\times$and$1.7\times$, respectively. Moreover, we show that the area savings of co-design permits the CPU to have 23% more cores and main memory, and that streamlining the LLC/main memory interface incurs a small 4% performance penalty.

CCS Concepts:• Hardware →Memory and dense storage;• Computer systems organization →Multicore architectures;

Additional Key Words and Phrases:Crosspoint architectures,ReRAM,on-die main memory systems

ACM Reference format:
Candace Walden, Devesh Singh, Meenatchi Jagasivamani, Shang Li, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce Jacob, and Donald Yeung. 2021. Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache.ACM Trans. Archit. Code Optim.18, 4, Article 48 (July 2021), 26 pages, DOI:https://doi.org/10.1145/3462632.