I used to get frustrated by the lack of metrics as well.
Then I realised we have some metrics in what is a very complex space, and maybe they are of limited use to me.
As we know the problem/opportunity of SCM is that it blurs the lines between memory and storage and memory makers and buyers could have vastly different requirements.
4DS has been positioned as a free standing non volatile memory and also as an embedded device in various applications. It may have IOT potential, but I'm not sure that is the focus for now.
The range of embedded applications could vary significantly from memory sticks in phones and cameras, SSD's used in computers and servers, system on chip, to switches for ASIC solutions etc.
Over the journey I've become less focused on the metrics and more focused on the process, the improvements and the reliability that lead to the building of the IP.
However, I take some comfort in the metrics that relate to endurance, as they seem to clearly point to improvements and reliability.
The TMT report of February 27 mentions 4DS achieved endurance in the millions of cycles and then goes onto make comparisons with NAND flash.
It mentions Single Level NAND flash cells (SLC) typically having endurance cycles of 100,000 cycles.
It also mentions Multi Level NAND flash cells having endurance cycles up to 10,000 cycles.
10 to the power of 4 = 10,000
10 ^ 5 = 100,000
10 ^ 6 = 1,000,000
10 ^ 7 = 10,000,000
10 ^ 8 = 100,000,000
The 4DS website outlines that NAND flash generally has very low endurance (from 10 ^ 3 to 10 ^ 4).
It also mentions DRAM endurance is extremely high - approx 10 ^ 15.
So back in February 4DS appear to have achieved 10 ^ 6.
Roll onto TMT's June 25 report and 4DS has achieved endurance cycles of tens of millions. Which would imply 10 ^ 7. The comment 'tens of millions" could mean anywhere between 20-90 million, but hopefully they are now aiming for 10 ^ 8 (100 million).
Importantly this was achieved whilst improving retention and without compromising speed (and demonstrating comparability with BEOL temperatures).
We now know that Lot 4 is about further optimisation along these lines.
That would be consistent with 4DS's long stated objectives:
1) DRAM like speed
2) As much endurance as possible without sacrificing speed
3) As much retention as possible without sacrificing speed and endurance.
Perhaps by demonstrating the repeat ability (and improvement) of the process over the different Lots, they are also showing how tunable the technology is in what they refer to as the vast opportunity space between DRAM and NAND flash.
Yes - they have kept quite on retention metrics, but the latest Patent for a memory device has a retention layer.
I think what's important about the two latest fast tracked patents is they both make specific reference to 4DS's past announcement about having read speed comparable to DRAM.
That goes some way to addressing the old chestnut that 4ds have constantly mentioned:
The ultimate market demand is therefore for Storage Class Memory with DRAM speed, the highest endurance achievable with this speed, a cost per gigabyte closer to NAND Flash, and a pragmatic retention far superior to DRAM retention.
It's easy to get lost in the complexities and opportunities that 4DS represents, so I often drift back to that above statement.
For me, I think cost becomes the issue, "a cost per gigabyte closer to NAND flash".
How is that achieved?
Partly by - realising we're looking at memory devices that have area much smaller than DRAM cells.
and
Perhaps - the manufacturing process for those memory devices is simpler? (It's harder to verify this).
I think 4DS has something quite special and will ultimately get there.
