Interesting angle this one I gotta agree KmT
Seems the Hashman is playing a little 3 card Monte with Punters by referring to the gate pitch value and not the node ref I assume.. ?
The link between the two having been disproportionate for some time, but when people speak about lowest geometries in relation to chip design they don't usually bang on about the pitch or gate length, now do they?
Thetechnology node(alsoprocess node,process technologyor simplynode) refers to a specificsemiconductor manufacturing processand its design rules. Different nodes often imply different circuit generations and architectures. Generally, the smaller the technology node means the smaller the feature size, producing smaller transistors which are both faster and more power-efficient. Historically, the process node name referred to a number of different features of a transistor including thegate lengthas well as M1 half-pitch. Most recently, due to various marketing and discrepancies among foundries, the number itself has lost the exact meaning it once held. Recent technology nodes such as22 nm,16 nm,14 nm, and10 nmrefer purely to a specific generation of chips made in a particular technology. It does not correspond to any gate length or half pitch. Nevertheless, the name convention has stuck and it's what the leading foundries call their nodes.
Since around 2017 node names have been entirely overtaken by marketing with some leading-edge foundries using node names ambiguously to represent slightly modified processes. Additionally, the size, density, and performance of the transistors among foundries no longer matches between foundries. For example, Intel's10 nmis comparable to foundries7 nmwhile Intel's7 nmis comparable to foundries5 nm.
It's more about the process scaling than any real measurement and has been for some time..
Scaling at which below 5nm, as per the chart above it gets a little tricky due to the Moore equation.
You'll also note in the slide above that at 3-2nm the devices change from FINFET to GAAFET and we usher in the nanosheet era, of which Samsung already has in announcing the 3nm chips using GAAFET tech
https://www.electronicsweekly.com/news/business/the-next-20-years-of-ic-evolution-2022-08/And if we copy the link containing the slide to review the full article we note the CEO of Imec clearly states;
Dennard scaling is no longer enough. “This one-dimensional version of the roadmap may not be sufficient anymore for the future,” said Van den hove (pictured) “we will have to tune our devices for specific applications.”
Future transistor architectures may include GAA devices built from a stack of nano sheets, den hove described several including a gate-all-around device built up of a stack of nanosheets and the forksheet device in which the N and the P channel transistors are moved closer together and the CFET where N and P transistors are stacked on top Of each other.
“This forksheet device, we see as an extension of the standard nano sheet concept, and we believe it will be introduced around the equivalent of the one nanometer generation,” said Van den hove
Before he goes on to say;
“It’s clear that you can realize another very important step in cell size shrinking, but obviously at the expense of much more complex contacting schemes to contact the source and drain areas. But we believe that we have developed integration schemes that would enable such transistors by optimizing the epi processes, patterning processes, and leveraging very sophisticated deposition processes to enable the contacting structures,” said Van den hove.
Possible ways ahead are reducing the thickness of the silicon channels to reduce channel length by replacing the silicon with
2D materials — atomically flat mono layers — such as tungsten or molybdenum sulfides or selenides.
“We’ve recently demonstrated the first versions of devices fabricated using 300 millimeter equipment,” he said.So you have the head of Imec stating they have recently demonstrated (i.e. constructed, fabricated, produced) the first versions of the devices which according to their very own road map would indicate 2D Nano or possibly even Forksheet materials in a GAAFET transistor device!!
I'm sorry but I can't read that any other way, can anyone?
So if IMEC have already demonstrated it (as they say) could that possibly mean that 4DS chips using fully crystalline PCMO material may have been stacked in 2D Nanosheets and arranged in a 3D monolithic array
I think it is reasonable to argue that it could possibly be a valid claim?
4DS TECHNICAL UPDATE
• New process breakthroughs have made 4DS’ Interface Switching ReRAM technology fully compatible
with
state-of-the-art high-volume DRAM and NAND production processes
• Third Non-Platform Lot wafers yielded an order of magnitude decrease in cell on-resistance, which
translates into an up to one order of magnitude boost in read speed
• Second Platform Lot wafers demonstrated
both device-scaling to imec’s minimum geometry and
memory switching with an access device on 300mm wafers using state-of-the-art production
equipment• Third Platform Lot utilizing imec’s megabit memory platform is planned to start late Q3 2021
4DS has for the first time demonstrated fabrication of fully crystalline Pr1-xCaxMnO3 (“PCMO”) at temperatures
compatible with the advanced processes run in today’s leading-edge high-volume memory DRAM and NAND
factories;− 4DS has demonstrated that this fully crystalline PCMO material reduces the cell on-resistance by an order of
magnitude compared to the PCMO material fabricated in the Second Non-Platform Lot. This reduction in cell
on-resistance directly translates into a significant improvement in read speed; and
− This significant performance improvement also means that full characterization (speed, endurance, retention)
of memory cells with this fully crystalline PCMO material requires memory cells operating in a memory array
where currents are controlled and limited by access devices.
And you gotta admit the new GAAFET Gate all Around offering is an advanced access device..
Leading edge trend
As shrinking becomes more complex, requiring more capital, expertise, and resources, the number of companies capable of providing leading edge fabrication has been steadily dropping. As of 2020, only three companies are now capable of fabricatingintegrated circuitson the most cutting edge process:Intel,Samsung, andTSMC.Basically production of semi conductor chips at these levels is a 3 horse race..
And Samsung, now partnered with Intel have beaten out TSMC to the latest node...
Samsung's 3 nm process is based onGAAFET(gate-all-around field-effect transistor) technology, a type ofmulti-gate MOSFETtechnology, while TSMC's 3 nm process will still useFinFET(fin field-effect transistor) technology,[10]despite TSMC developing GAAFET transistors.[11]Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (multi-bridge channel field-effect transistor).[12]Intel's 3 nm process (dubbed "Intel 3" without the "nm" suffix) will use a refined, enhanced and optimized version of FinFET technology compared to its previous process nodes in terms of performance gained per watt, use of EUV lithography and power and area improvement.[13]
The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of theInternational Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.[14]However, in real world commercial practice, "3 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption,[15][16]Moreover, there is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node.
So to be fair, whenever we bang on about the minimum geometry at Imec & in relation to to the roadmap put forward it is reasonable to speak in relation to the node and little else I'd assume, others can always disagree if they choose..
I would also like to think that if IMEC not long ago demonstrated "versions of devices" than as a leading edge institute you might assume they were referring to the 3 or possibly 2nm node ( I mean they did tape out 3nm chips in 2018 as stated) using GAAFET devices and by way of association 2D nanosheet materials stacked in a 3D monolithic array in order to achieve the benefits stated;
"This reduction in cell on-resistance directly translates into a significant improvement in read speed"
"This significant performance improvement also means that full characterization (speed, endurance, retention)of memory cells with this fully crystalline PCMO material requires memory cells operating in a memory array where currents are controlled and limited by access devices."
Because if it doesn't then they were wasting their time and testing a good 12 months of shareholder patience as neither are/were required to produce a normal working CMOS megabit memory chip at 20/22nm FFS!!
Commercialization history[edit]
In late 2016,TSMCannounced plans to construct a 5 nm–3 nm nodesemiconductor fabrication plantwith a co-commitment investment of around US$15.7 billion.[28]
In 2017, TSMC announced it was to begin construction of the 3 nmsemiconductor fabrication plantat theTainan Science Parkin Taiwan.[29]TSMC plans to start volume production of the 3 nm process node in 2023.[30][31][32][33][34]
In early 2018, IMEC (Interuniversity Microelectronics Centre) and Cadence stated they had taped out 3 nm test chips, usingextreme ultraviolet lithography(EUV) and 193 nmimmersion lithography.[35]
In early 2019,Samsungpresented plans to manufacture 3 nmGAAFET(gate-all-aroundfield-effect transistors) at the 3 nm node in 2021, using its own MBCFET transistor structure that uses nanosheets; delivering a 35% performance increase, 50% power reduction and a 45% reduction in area when compared with 7 nm.[36][37][38]Samsung's semiconductor roadmap also included products at 8, 7, 6, 5, and 4 nm 'nodes'.[39][40]
In December 2019, Intel announced plans for 3 nm production in 2025.[41]
In January 2020, Samsung announced the production of the world's first 3 nm GAAFET process prototype, and said that it is targeting mass production in 2021.[42]
In August 2020, TSMC announced details of its N3 3 nm process, which is new rather than being an improvement over its N5 5 nm process.[43]Compared with the N5 process, the N3 process should offer a 10–15% (1.10–1.15×) increase in performance, or a 25–35% (1.25–1.35×) decrease in power consumption, with a 1.7× increase in logic density (a scaling factor of 0.58), a 20% increase (0.8 scaling factor) in SRAM cell density, and a 10% increase in analog circuitry density. Since many designs include considerably more SRAM than logic, (a common ratio being 70% SRAM to 30% logic) die shrinks are expected to only be of around 26%. TSMC plans volume production in the second half of 2022.[1]
In July 2021, Intel presented brand new process technology roadmap, according to which Intel 3 process, the company's second node to use EUV and the last one to use FinFET before switching to Intel's RibbonFET transistor architecture, is now scheduled to enter product manufacturing phase in H2 2023.[7]
22 July 2021
In October 2021, Samsung adjusted earlier plans and announced that the company is scheduled to start producing its customers’ first 3 nm-based chip designs in the first half of 2022, while its second generation of 3 nm is expected in 2023.[4]
In June 2022, Samsung started "initial" production of a low-power, high-performance chip using 3 nm process technology with GAA architecture.[44][45]According to industry sources, Qualcomm has reserved some of 3 nm production capacity from Samsung.[46]
On July 25, 2022, Samsung celebrated the first shipment of 3 nm Gate-All-Around chips to a Chinese cryptocurrency mining firm PanSemi.[47][48][49][50]It was revealed that the newly introduced 3 nm MBCFET process technology offers 16% higher transistor density,[51]23% higher performance or 45% lower power draw compared to an unspecified 5 nm process technology.[52]Goals for the second-generation 3 nm process technology include up to 35% higher transistor density,[51]further reduction of power draw by up to 50% or higher performance by 30%.[52][53][51]
@Brabant90 Hey Brabs, you wanna look into something then have a look at Samsungs patent history around the timelines shown when they leap frogged TSMC. 2D Nano, BSPDN, 3D Monolithic, Memristor etc etc
@Acca Total coincidence the timings I'm sure ;-)
@hashtagyolo Not sure why you are p***ing wind brother, we're all on the same train aren't we?
@chirofalls Soon brother, we hope, soon
@Nutsy If it drifts fill ya boots champ
@jasp you're possibly gonna need a bigger island
@mjshackl Does that seem a fair and reasonable engineering assumption brother? Conspiracy theories aside of course, just a bit of fun really.. ;-)
(20min delay)
