Folks the issue is not with the memory cell it’s an issue with integrating the memory cell using small dimension (5nm) to imec’s megabit memory array.
4DS Memory are comparing differences in results of the Second Platform Lot and Third Platform Lot (The unexpected issue was not apparent in the Second Platform Lot).
It’s likely back to optimising one, two or three of the 100 mask templates to get back where we need to be.
What I did not like in the announcement was the “long term” delay comment. How long is a piece of string.
Very poorly communicated and compounded the fall of the share price. So much for improving announcements, this needs to be addressed.
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