@mjshackl &
@Flectional (because you are both considered "technical" by the people here;
I've been thinking a lot about your reply to my post, and whilst everything you said is true, it was explaining to me about how resistive ram works, because mj assumed that i did not understand that, because I was talking about "dielectric effects of scaling down"
mj's post got a lot of likes and upvotes from people so im assuming they found value in his explanation of how resistive ram works:
but there is a problem here, and that problem is that people who completely missed my point, as mj apparently did, would think that mj's explanation eliminates my point.
so to clarify, here is a more detailed explanation of my point, explained in plain language the way MJ did.
resistive ram is contains an array of cells. those cells are etched into a substrate, and the walls between those cells are an insulator.
as you scale down, that insulator gets thinner and thinner.
when you "write" to a resistive cell, as previously explained you apply a voltage, which causes a migration of ions, causing a semi permanent change in resistance.
while you are "writing" that cell, the difference in voltage in your cell, and the adjacent cells means that across the insulating wall between them there is a dielectric stress, ( a bending of insulator due to voltage applying pressure on it) this is called "parasitic capacitance" because it is unintended.
what can happen as a result of this, is that you can have unintended effects on the cell.
there is a lot of documentation out there for anyone who wants to actually research this, but Its a known, well understood effect of scaling down memory arrays, and there has been research specifically related to resistive ram that i posted (completely ignored by everyone btw).
parasitic effects are a genuine, well documented effect of scaling.
don't believe me? let me google that for you
https://www.google.com/search?q=parasitic+capacitance+reram
