I followed the link in your post ... and looking at the subject...

I followed the link in your post ... and looking at the subject without any information regarding the particular characteristics of the cell type or operating parameters, I did not see any issues noted with the scaling of cells apart from the fact that it may limit the array size. I do not see this as an issue - in fact it would probably be a necessity anyway, given that trunk conductor paths would become larger by proportion as the cell size reduces unless the array size is reduced to suit.

Capacitance is a characteristic which needs to be dealt with with any cell type, not just re-ram, and not just 4DS re-ram, when these incredible cell sizes are contemplated; it is a basic characteristic of all electrical circuits

Pointing at 4DS and inferring that it is somehow subject to issues that are not present with any other memory cell with respect to scaling does not strike me as an argument with any merit. It is not a characteristic of the cell type, but rather an issue that needs to be dealt with in any micro-scaling array.

I do not see the point you are trying to make. Taking generalised research papers discussing the barriers to re-ram cell scaling does not provide any basis to your argument.