4DS switch only memory will:- clear DRAM data bottleneck -...

4DS switch only memory will:
- clear DRAM data bottleneck
- mitigate DRAM operation inefficiencies such as bit flip rewrite and static operationv/ excessive energy use and resulting poor memory cache utilisation / single sub array 'mats' operate at 40% capacity at present - apply 4DS som and they will operate at capacity = 95%
- the ability to partition the 4DS SOM in a DRAM application ( parallel to DRAM not replacing it) allows power sensitive blocks / modules to operate in conjunction with each other which is an essential application operation in AI accelerator chips - these chips will replace the GPU
This partitioning allows multiple block/module reuse potentially up to 10,000 times in a single design use so a 1KmW power saving in that partition under those conditions would result in a 10KmW power saving in current applications

combine these 2 apsects alone ( memory at capacity and the ability to partition) and you have a application use worth $$$$$$$ to the DRAM acquirer of this tech

20nm success is key to the above obviously