4DS - Anything but Charting, page-30267

the heating and cooling cycles under manufacture will display relative variation in the die of amorphous / crystalline pcmo ( and others) relative to their wafer location - centre, body and/or edge - add to that the number of die per wafer from a 60nm node compared to a 20nm node

amorphous material has a very random structure with a low expansion coefficient than crystalline material which is inherently a highly organised structure so die cracks are to be expected in any first run at 20nm - obviously just my opinion but first time run success with the above in mind would be amazing.
the first run will set the parameters for the design 'fixability' to be incorporated and set the path to the optimal yield outcome in following lot manufacture

fair to say there is increasing confidence in this technology as the use case has shifted to switch only memory and the market application for such a tech is huge along side DRAM and AI accelerators
personally I think Ting should be credited with this development achievement - and of course IMEC

as we know - 20nm success is the key and it appears increasing likely - i think first run 20nm will lay the ground for that success in following lots

just my view though - one among many as always