4DS - Anything but Charting, page-30525

IMEC run parametric tests as the process flow progresses during manufacture:
'Parametric testing usually consists of forcing a constant voltage at a node and measuring the current response (force-voltage-measure-current, or FVMC) at that node, or forcing a constant current at a node and measuring the voltage response (force-current-measure-voltage, or FCMV).'

So I'de imagine some boel work does get completed in the facility -

Integral steps in BEOL:
1. Additional Metal Layers: - Multiple layers of metal are added to enhance the interconnections. - This ensures that the chip can handle complex tasks and high speeds.

2. Passivation: - A protective layer is applied to shield the chip from environmental damage.

3. Testing: - The chip is rigorously tested to ensure it meets all specifications.

4. Dicing: - The wafer is cut into individual chips, each ready to be packaged and used in electronic devices.

I'm only guessing of course.