4DS - Anything but Charting, page-30550

Umm. No. PL5 & PL6 are separate events. PL5 @ 60nm is to test different configs and see what performance improvements / differences are achieved from different tunings. They already noted that there were a variety of performance differences and tradeoffs that could be achieved for speed, retention, durability, etc. PL5 is to discover what those limits might be. PL6 is to test the 20nm scale down of (probably) the most general purpose set of tunings. PL5 and PL6 are unrelated. They in fact noted that PL5 would inform the decisions around config for PL6, but I can't see how that can be the case as I would expedct PL6 etchings to be already in the works by the time PL5 comes out, and almost certainly by the time PL5 testing is complete, but perhaps I am being too conservative there. At least that is my understanding from the flow of briefing sessions and news releases from the company. Whether they can shrink to 20nm or not for PL6 has never been linked to whether they will be doing and shipping the PL5 run. In the past IMEC have shipped the chips regardless of whether the chips achieved the primary end point as testing can reveal important information for the next run, and in fact is essential in a failure case to learn what went wrong and how to prevent it next time.