I'll be a little more up front though I'm not spruiking anything as a certainty :
HBM4 being brought forward asap as manufacturers suspect the forecasted Gen AI boom will leave the incoming Nividia GPUs' short...they'll need the HBM sooner
the HBM4 stack is designed to mitigate/bypass DRAM capacity and bandwidth limits by stacking the memory dies on top of a logic layer and having interconnecting TSV channels all hooked up to a GPU achieving higher bandwdith - thats' the relevance of the new JEDEC standard
This is the perfect ( one of many) use case application for 4DS switch only memory
that's the other reason it hinges on a successful 20nm outcome imo
just my view
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I'll be a little more up front though I'm not spruiking anything...
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