great explanation
further to that as a rider:
Dram die read disturbance is the issue - (bottle neck choking data flow) best mitigation practice atm is refresh management command (RFM) initiated by the memory controller periodically when the row activation number becomes 'scrambled' or exceeds a preset limit
this is being superseded by 'per row activation counting' (PRAC) which initiates off a backup signal from the dram to the memory controller and 'forces' the controller to cease serving requests and to issue rfm commands
highly inefficient in its best format and energy hungry though 'better' than rfm alone ...4DS chip potentially mitigates the whole process if successful manufacture is achieved.
will be interesting to see if 4DS is covered at the FMS underway now? - hope so
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