4DS - Anything but Charting, page-31303

yeah, quite clear now - key take aways for mine; ( as a time waster of course)

looking 'to prove out' the cell in specific applications with an advanced cmos partner
'most likely' will not scale in the x-y dimension (PH words) indicates it will not scale beyond 20nm - stated reason is increasing the density will affect performance values across the cell ( needed to know that and it is not in any literature but PH made it clear - previous pcmo development by others determined this also which is why no previous went further with it- see previous posts here in the threads )
- the memory will need to adapt to the scaling of the attached circuitry in the specific application under design - those areas are AI coherence processing / embedded / MCs' and ASICs' - these are the 'prove out' areas PH is talking about and these are years away with many miles of bench testing and qually - happy to be corrected
cross bar with selector is a possibility
As Sally stated it remains an R&D project at this point

success at 20nm is still the desired outcome to gateway the path forward - IMEC will need to be a central third party in that pathway forward imo
'liquidity event' is some time away imo

looking forward to the PL5 data indicating the process improvements for now