- can't complete design and architecture on 60 if pl5 was a failure - ie no process improvement on manufacturing outcomes ie parametric read outs and defect density = improved yield metrics - no complete platform access available - the above 2 mean verification is nowhere in sight - no physical chip design possible due to 3 above - no completed mask generation so no physical design blueprint available to proceed as above 4 incomplete - at this point we can shorten this process to bullit points as they all interplay on the success of previous process step so.... no complete characterised photolith, etch ( whatever process they are using), doping ion implantation, then assembly and packaging.
phew!
so then package.... - die attach followed by wire bonding then encapsulation then final testing and quality assurance
pretty much lunch money would do it imo at this stage if pl5/6 are a dud
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