yeah -hasn't happened yet
from pl6 outcome
- 20nm manufacture must be right - mask / etch - annealing ( which historically impacts mask/ etch so pl5 learnings here will or won't show their value)- clean side wall and surface - yield / defect density ( ydd is a key cost advantage metric on test volume outcome as to revenue numbers per previous post)
- parametric testing from imec on the manufacture must be right
- calcium ion doping must be right
- operational test data at that point should look like pl4
etc
then infineon 'platform' work must be successful to allow test chip design (15 months )
then technology transfer to foundry (12 month minimum to mix bake and test on an advanced cmos line ) and the cost of that transfer process
then possibly volume test run
and most likely a few forks in the road yet along that path
just my view - nothing more
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