4DS - Anything but Charting, page-33739

Yeah agree, hence I said "takes input from"...

I think it's a moot point anyway. I don't think there is a separate 60nm and 20nm version of the Infineon product... I base this off the Universal Memory platform at imec which is being used for both 60 and 20nm (granted it's capabilities are limited when it comes to some of the unique 4DS characteristics) - it's one imec "platform" for both geometries.

Whether the Infineon design identical or different, my take is the macro controller doesn't carry much risk of being compatible at 60nm and incompatible at 20nm. What the controller has to do to program the memory cells is largely the same at both geometries (the underlying physics is the same). What changes is likely things like programming times, power applied to write to the cell which seems like the simpler end of things to solve in this whole process. I recall this type of programming variability was something PH discussed in briefings early last year as something they might be able to do on the same chip (so a customer could achieve different performance characteristics on the same chip!).

We've heard that PL5 has already moved forward with a memory stack adjustment in readiness for PL6 - so again this would be helpful for the Infineon design.

Someone posted here that Infineon would likely do a "digital twin" - if that's the case this seems like the kind of thing they would be moving forward with right now, taking input from PL4 and PL5 to guide the design process.

This whole Infineon process, to me, appears to carry far less risk than scaling the memory cell itself. They've paid a lot of money not necessarily because it's earth shatteringly complex, but the value released by the design outcome is significant. Infineon know this, and they are chasing 4DS top dollar to own the IP at the end of the engagement.