@Khoutam the latest revision of the road map looks like management decided they didn't want market (or infer) the prospect of a PL6 fail by suggesting "manufacturing & testing of validation lot at IMEC" which might have required the timeline to be stretched / extended yet again (i.e. Memory Test Chip fabrication & testing expected in 2H 2027).
Best-case scenario marketing would be my guess for the recent roadmap revision (while keeping in mind a tried & tested saying that's also coincidentally very characteristic of 4DS generally when viewed from a variety of perspectives inclusive of product development & cap raises)..."there's many a slip 'twixt the cup & the lip".
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