it is - hopium + sentiment often drives fomo
the mechanics of 'preliminary analysis' are worth understanding
this is not testing performance metrics at this stage
it is gathering data on the manufacturing process at 20nm comparative to pl5 scaled stack and pl4 60nm.
perhaps the fact we are x many weeks into this analysis is a hint to the narrative to come
this prelim analysis is required to determine the extent of the material variabilities post manufacture as they present at each lot outcome and assist operational analysis - this research assists further development
what might those variabilities be?
1) the set operation in the memory occurs on applied voltage (Vth) allowing nucleation of the pcmo crystallisation and its growth and essentially the magnitude of the voltage pulse correlates to switching speed at the expense of retention time.
( STmicro turned down the voltage magnitude in their pcm 'stella' to 80ns program speed to achieve a 1 hour retention time at 150 deg - stored values dissipate beyond that window and with temperature variations)
This relationship changes as you scale quite markedly due to the altered material composition at each node.2) etch / mask ? hard side wall and clean surface /field ? .....it's a punt no question
3) testing cannot be fully characterised until infins platform is built by imec to access the cells in total - that is going back to the Voltage magnitude and establishing whether or not the 'crystallisation' has uniformity across all cells and uniformity across switching operation for write time and write termination - there is a window temperature which must be maintained during programming / voltage application and it must match the crystallisation on that same voltage - etch/mask and doping are also significant 'change factors as you scale which will also introduve significant differentiation from the baseline as simulated - at 20nm these outcomes will be different to 20nm scaled stack and the 60nm lot - that is certain imo.
not going to ramble on too much but to be clear only - dynamic programmability is not a new 'thing' - it is well understood in pcms' that you must turn down voltage magnitude / ie speed to gain retention window optimum and there must be 'life cycle operability' set/ reset operation combined with smooth transition between poly amorphous and crystalline state ( on/ off swathing) across the complete area of the cells
@Troykaneed a test chip imo before the cartel or anyone even remotely gets serious and wants a close look imo
those hitting chat gpt / generative AI can put some of this ramble above in and see what comes back - it might illuminate where things are at - i don't know as I don't use it but it may be helpful
waiting to see what the company has to say in a few more weeks when prelim is complete and the path forward can be clearly flagged on the contract terms to either build the access platform because its at that stage or pl7 is required to hit a definitive operational test chip
no fomo or anything else - just waiting for solid news
objectivity will arrive when there is something to release
of course I could be way wrong and it may be working like a beast - either is possible
glah
(20min delay)