Some great analysis going on here. I think best to stick with...

Some great analysis going on here. I think best to stick with existing public info - slide 14 from cap raise presentation, best illustrates where responsibilities sit, for design, tape-out, front/back end fabrication, etc. There are lots of moving parts here - lets hope they get 20nm correct (I'm led to believe much of the hardwork ensuring paramaters are as close as possible to correct; was done in the 5th platform lot). I think many have underestimated the significance of PL5, being the 'bridge' to derisk the build of PL6.

https://www.4dsmemory.com/wp-content/uploads/2025/02/4DS-Memory-Capital-Raising-Presentation-January-2025-1.pdf



Also, something that has been rattling around in my head for the last year was a question/answer during attendance at the GoldCoast investor roadshow in 2024 - the question was "why can't imec put out an announcement about us, to spread the word publically about what 4DS has accomplished? (with PL4)". The response from DM was "Imec reviews and approves any of the technical announcements we provide to the market" (or something to that effect). Now keep in mind in a recent announcement it was stated "...If the Company is succesful in scaling to a 20nm memory cell array, then the sixth platform lot will position 4DS area-based interface switching reram technology as a potential generational memory". This is a statement that Imec has clearly been comfortable to be communicated given that GC question (which gives me quiet confidence in what we are doing). Time will tell. A succesful 20nm means we are at least on the verge of industry significance (for scale at least) - other detailed characterisation will require the custom test chip.