The below chart gives us insight into the widening Memory Wall gap between compute performance and memory bandwidth. From the days of Intel Pentium 2 to NVIDIA H100, compute power has grown exponentially, but conventional memory technologies built on recycled architecture have failed to close the gap. 4DS Memory’s ultra fast read/write speeds, single-shot programming and minimal error correction requirements can overcome the Memory Wall.
DRAM followed the path of Moore’s Law for many decades. Gordan Moore coined the term and his economic prediction about density and cost of transistors generally held true until 2009 for DRAM. Since 2012, cost of DRAM has barely improved. This is a direct result to DRAM’s 1T1C physical limitations and manufacturing complexities.
4DS Memory is based on 4F2 cell structure, the smallest cell layout in advanced memory designs. Smaller cell area means more memory cell per unit area, more usable dies per wafer, lower cost per bit.
Folks, once 20nm is announced in the next few weeks, the dynamics of 4DS as we know it will fundamentally change.
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