I haven't read the google stuff, but basics of magnetic field theory give you a couple of pointers.
1. Magnetic fields are only produced by the movement of electric charge through a conductor. The larger the charge movement (current) the larger the field. 4DS current flow is lower than normal memory chips, and therefore should be less susceptible to the alien crosstalk which occurs between neighbouring cells.
2. The lower current flows (and power usage) means that there is less impact on neighbouring cells of interference of any form, as the voltage fluctuations caused by the cycles are lower.
2. Magnetic fields are propagated and retained in materials with strong affinity to electric fields (ie good conductors). The dielectric material utilised within the chip is a poor conductor (hence the low current requirement of the chip), and therefore produce a lower magnetic flux density for a given movement of charge.
3. Chips are identical components inserted into an array. Thus, where there are filaments inserted as part of the array structure, they are all in the same location, and would reinforce the fields produced by the adjacent cell. 4DS chips recreate the filament for each change of state, and then it dissipates. The filaments are formed in random locations within the cell, and therefore will not provide such reinforcement.
4. The data rate for given chip activations is a fraction of that in DDR technology - with no error checking required and one-time activation, if the same problem manifested itself it would occur at a data rate some 20 times (from my vague recollection) that of current DDR chips - there is no rewrite required.
I'm a little rusty on the specifics of the chip … only been back in for a couple of weeks.
Anyways, methinks it is a non-issue.
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