4DS - Anything but Charting, page-9488

I can't remember anything being discussed about what the current wafer iteration is all about - if a platform iteration is currently underway with a "recipe" that meets SCM requirements - would IMEC be looking at a different "tune" with this wafer lot? Like something that isn't as fast as DRAM, but would be more suitable for general solid state storage? (with performance benefits over FLASH of course).

Saying that the tech is tunable is one thing, to actually demonstrate that it is in a fab equivalent process is another altogether.