Yep, from Rubber Dildoes to Rockets... As they say the space between DRAm & Flash is huge Crom... hahaha
Georgia Tech/TSMC ReRAM Compute-in-Memory Features
The researchers developed a ReRAM-based macro IP for a neural network application, with the ReRAM array itself providing the MAC operations for a network node, and supporting circuitry providing the analog-to-digital conversion and the remaining shift-and-add logic functionality.
The overall implementation also incorporated three specific features to address ReRAM technology issues associated with: HRS and LRS variation; low (HRS/LRS) ratio; and, HRS drift.low HRS/LRS ratioOne method for measuring the sum of the data inputs to the node multiplied times a weight bit is to sense the resulting bitline current drawn by the cells whose data/wordline = ‘1’. (Note that unlike a conventional SRAM block with a single active decoded address wordline, the ReRAM compute-in-memory approach will have an active wordline for each data input to the network node whose value is ‘1’.
This necessitates considerable additional focus on read-disturb noise on adjacent, unselected rows or the array.) However, for a low HRS/LRS ratio, the bitline current contribution from cells where data = ‘1’ and weight = ‘0’ needs to be considered. For example, if (HRS/LRS) = 8, the cumulative bitline current of eight (data = ‘1’ X weight = ‘0’) products will be equivalent to one LRS current (‘1’ X ‘1’), a binary multiplication error.The researchers chose to use an alternative method. Rather than sensing the bitline current (e.g., charging a capacitor for a known duration to develop a readout voltage), the researchers pumped a current into the active bitcells and measured Vbitline directly, as illustrated below.The effective resistance is the parallel combination of the active LRS and HRS cells.
The unique feature is that the current source value is not constant, but is varied with the number of active wordlines – each active wordline also connects to an additional current source input. Feedback from Vbitline to each current source branch is also used, as shown below.This feedback loop increases the sensitivity of each current source branch to Reffective, thus amplifying the resistance contribution of each (parallel) LRS cell on the bitline, and reducing the contribution of each (parallel) HRS cell.
The figure below illustrates how the feedback loop fanout to each current branch improves the linearity of the Vbitline response, with an increasing number of LHS cells accessed (and thus, parallel LRS resistances contributing to Rtotal).LRS/HRS variationAs alluded to earlier, multiple iterations of write-read are often used, to confirm the written value into the ReRAM cell.The technique employed here to ensure a tight tolerance on the written HRS and LRS value evaluates the digital value read after the write, and increases/decreases the pulse width of the subsequent (reset/set) write cycle iteration until the (resistance) target is reached, ending the write cycle.
HRS driftThe drift in HRS resistance after many read cycles is illustrated below (measured at high operating conditions to accelerate the mechanism).To compensate for the drift, each bitcell is periodically read – any HRS cell value which has changed beyond a pre-defined limit will receive a new reset write cycle to restore its HRS value. (The researchers did not discuss whether this “mini-reset” HRS write cycle has an impact on the overall ReRAM endurance.)Testsite Measurement DataA micrograph of the ReRAM compute-in-memory testsite (with specs) is shown below.SummaryReRAM technology offers a unique opportunity for computing-in-memory architectures, with the array providing the node (data * weight) MAC calculation.
The researchers at Georgia Tech and TSMC developed a ReRAM testsite with additional features to address some of the technology issues:HRS/LRS variation: multiple write-read cycles with HRS/LRS sensing are usedlow HRS/LRS ratio: a Vbitline voltage-sense approach is used, with a variable bitline current source (with high gain feedback)HRS drift: bitcell resistance is read periodically, and a reset write sequence applied if the read HRS value drops below a threshold
The author goes on to state, "I would encourage you to review their ISSCC presentation".
Highly desireable for a reason.. Well, actually many reasons
And again a similar study at Stanford, where our friend Ting is studying his PHD has also had a crack..
And
Challenges and Applications of EmergingNonvolatile Memory DevicesWritam BanerjeeCenter for Single Atom-based Semiconductor Device, Department of Material Science and Engineering,Pohang University of Science and Technology (POSTECH), Published: 22 June 2020
More precisely, this review explainsthe journey and device engineering of RRAM with various architectures. The challenges in differentprototype and eNVM devices is disused with the conventional and novel application areas. Compareto other technologies, RRAM is the most promising approach which can be applicable as high-densitymemory, storage class memory, neuromorphic computing, and also in hardware security.
Brain-inspired computing, i.e., neuromorphic computing, is one of the emerging novel functionalities beyond memory space. As compared to today’s von Neumann computers, brain can perform complex tasks, such as recognition, inference, etc., with minimal power consumption. The well-known learning rule in neural network is spike-time-dependent plasticity (STDP), which is the synaptic weight modification by the pre- and post-synapse timing difference. In such applications, because of the good scalability and low power consumption, eNVM devices can achieve the synaptic
density closer to the density in brain (~ 1010/cm2).
Both the PCM and RRAM are the major eNVMs in this category. In RRAM, the switching can be abrupt or analog type. For neuromorphic computing,
a precise change of conductance is essential; hence, analog switching is very useful. Integration of such a device with CMOS technology would be a problem-solver associated with artificial intelligence.
For neuromorphic applications, a high-density, low-power device with at least
5bits/cell storage is necessary.
A prototype of such RRAM-based neural network of 8×8 1T1R array in the Ag-doped SiOxNy structure is shown in Figure 13a–c [131]. The synaptic weight update was demonstrated with special learning protocol and peripheral circuit design (Figure 13d–f). The research also identified the possibility to emulate both the short-term and long-term synaptic plasticity by using Ag-doped RRAM devices based on MgOx, SiOxNy, and HfOx. Figure 13g shows the paired-pulse measurement, and Figure 13h shows the STDP in such device. However, sometime gradual transition of resistance state is difficult during the SET of RRAM and RESET of PCM. New device engineering with “2-PCM” synapse is also proposed [132]
STT-MRAM, phase-change memory (PCM) and resistive RAM (ReRAM) are among the new memory types in production today. Each technology is different and targeted for various applications.
Intel’s 3D XPoint technology is one example of PCM. PCM stores information in the amorphous and crystalline phases. ReRAM is based on the electronic switching of a resistor element.
However;
Phase change RAM (PCRAM) and resistive RAM are somewhat simpler to construct than MRAM. PCRAM stores its bit as the crystal state of material, which is resistive in its amorphous state and more conductive in its crystalline state. RRAM’s information is also stored as a resistance, but it changes according to a conductive bridge that forms through an otherwise resistive material.
The Endura Impluse, Applied’s solution for those two memory technologies, is also a nine-PVD machine with integrated metrology.
The company already manufactures chips for stand-alone MRAM producer Everspin, which recently began pilot production of a 1-gigabit chip.
GlobalFoundries isn’t alone among the majors in embedding MRAM, of course. TSMC, Intel, and Samsung have also developed it.
Samsung is already shipping supposedly and Global Foundaries (Who's CEO was just hired by WDC) is too, though sourc3es aren't saying..
Samsung announced that it has started to mass produce its first embedded MRAM, made using the company's 28nm FD-SOI process. Samsung says that its eMRAM memory module offers higher performance and endurance when compared to eFlash, and can be integrated into existing chips.Samsung eMRAM imageSamsung details that its eMRAM is 1,000 times faster than its eFlash memory, and it does not require an erase cycle before writing data (unlike Flash memory). The voltage used is also lower - and in total eMRAM consumes 1/400 the energy compared to eFlash for the writing process.
Samsung's MRAM capacity, though, is lower than its 3D Xpoint, DRAM and NAND flash.Samsung did not disclose the capacity of its first eMRAM module and its first customer. As Samsung says that it will only tape out its 1Gb eMRAM in 2019, it means that this first eMRAM capacity is lower than 1Gb. Samsung also says that it plans to adopt its eMRAM for its 18nm process in the future too.Mar 08, 2019 by Ron MertensLog in to post comments
IMEC: STT-MRAM is suitable for 5 nm last level cache, offers significant energy gains over SRAM in large memory densitiesResearchers at Belgium-based research institute Imec presented the first power-performance area comparison between SRAM and STT-MRAM last-level cache at the 5 nm node.
The analysis, based on design-technology co-optimization and silicon verified models, reveals that STT-MRAM meets the performance requirements for last-level caches in the high-performance computing domain. For larger memory densities, STT-MRAM was found to offer significant energy gains compared to SRAM. Dec 04, 2018 by Ron Mertens
PCM, MRAM & RERAM aren't all that different really and in fact MRAM has Mott's name all over it...
The potential for control of ferromagnetic switching through electronic spins was first proposed by Nevill Mott in 1936 and was experimentally demonstrated by Albert Fert in 1968. In 1988, the discovery of the giant magnetoresistance effect launched the field of spintronics and its applications in magnetic media.
And in fact HGST B.V have a patent in that covers switching an MRAM cell in to a RERAM cell and back if and as required..
SELF-RECOVERY MAGNETIC RANDOM ACCESS MEMORY UNIT
The present disclosure generally relates to spin-torque-transfer magnetoresistive random access memory (STT-MRAM) memory cells. In the magnetic tunnel junction (MTJ) of the STT-MRAM memory cell, a 1 nm thick barrier layer having a triclinic crystalline structure is doped with B, N, or C. By applying a positive voltage to the MTJ, the magnetic state of the free layer of the MTJ may be switched.
By increasing the voltage applied to the MTJ, the MTJ may change to operate as a ReRAM memory cell, and the crystalline structure of the barrier layer may switch to monoclinic. Before reaching the breakdown voltage, a negative voltage may be applied to the MTJ to switch the crystalline structure of the barrier layer back to triclinic. Once the negative voltage is applied and the crystalline structure of the barrier layer is changed back to triclinic, the MTJ may function as a STT-MRAM cell once again.
he Gibbs-free-energy-modulation-based working principle is the driving force of writing and reading operations of the Mott memory devices. If the kinetic energy barrier is higher than the thermodynamicdriving force, the device can experience a stable metastable state “1”, and the memory behaves aseNVM one (Figure 5d). In reverse, for a small kinetic energy barrier, the memory behaves as VM one(Figure 5e). The behavior is also thermally dependent. It is also possible to realize VM and NVMoperations within a single material system in optimized temperatures.
So you could actually use RERAM as a volatile memory if you wished... But why? Well...
As compared to DRAM andSRAM memories, the major advantage of Mott memories is its two-terminal design with cross-pointarray with 4F2cell area size (F is the minimum chip feature size) with faster Mott transitions than Flash.
Much greater density and lower power useage whilst in use..
In fact you
"This work investigates the performance of RRAM based Non-Volatile SRAM (NV-SRAM) cells. The architecture of NV-SRAM includes a 6T SRAM cell and a couple of one transistor-one resistive memory devices configuration. RRAM is controlled by MOSFETs in 1T1R configuration. The performance of NV-SRAM cell is investigated by circuit simulation with a SPICE compact model of oxide-based resistive random access memory based on the conductive filament evolution model".
"The personal mobile device is one of the most important products in the market of commercial electronics. Battery-powered mobile chips are faced with the challenge of low power operation and rapid, reliable data back-up in the event of a sudden power failure. Nonvolatile memory (NVM) enables a mobile chip to turn off its power supply to further reduce standby power and extend battery life without a loss of data".
Published in: 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
The reason for doing so is perfectly clear.... Just in case Cookie swings by for a chat and to discuss how much F***ing power these new 5G smart phone apps draw from his poor old slimline batt Elon slung him from factory second stockpiles.. hahaha
| 1. Samsung: | Units Shipped: 315 million |
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| 1 | x | Profit: USD 18,947 million |
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| 2 | 2. Apple: | Units Shipped: 215 million |
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| 3 | x | Profit: USD 48,351 million |
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| 4 | 3. Huawei: | Units Shipped: 152 million |
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| 5 | x | Profit: USD 6,890 million |
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| 6 | 4. Oppo: | Units Shipped: 111 million |
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| 7 | x | Profit: USD 1,400 million |
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| 8 | 5. Vivo: | Units Shipped: 95 million |
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| 9 | x | Profit: USD 1,125 million |
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| 10 | 6. Xiaomi: | Units Shipped: 95 million |
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| 11 | x | Profit: USD 1,000 million |
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| 12 | 7. LG: | Units Shipped: 55 million |
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| 13 |
| Profit: USD 110 million |
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| 14 | 8. Lenovo: | Units Shipped: 50 million |
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| 15 | x | Profit: USD 535 million |
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| 16 | 9. ZTE: | Units Shipped: 45 million |
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| 17 |
| Profit: USD 719 million |
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| 18 | 10. Alcatel Lucent: | Units Shipped: 20 million |
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| 19 | x | Profit: USD 218 million |
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And did anymore get the memo that the CEO of Global Foundaries has taken a part time hussle at WDC? Covid, second job, I get cause everyone is hurting just that little bit extra.
The Dige, rules the henhouse by being the smartest god damn chicken weasel that ever lived...
Ol Fog Horn be proud, Boy, I say boy.... You don't go runnin madly into a new henhouse... No... ! Hell you rile all dem clucky duckies up boy....
No son... You aint gettin no sweet bumnuts that way... You got to slide on in there a little, smile and cuddle em a bit as you enter the room.. hehehe ;-)
Western Digital Appoints Dr. Thomas Caulfield and Miyuki Suzuki to Its Board of DirectorsSAN JOSE, Calif. - Jul 8, 2021Western Digital Corp. (NASDAQ: WDC) today announced that Dr. Thomas (Tom) Caulfield and Miyuki Suzuki have been appointed to its board of directors effective July 6, 2021. Caulfield,
currently CEO of GLOBALFOUNDRIES® and Suzuki, a Japanese-based, Fortune 100 business leader, bring semiconductor and global operating experience that complements Western Digital's growth and innovation strategy.
"
With semiconductor operations across the Asia-Pacific region including our joint venture with Kioxia in Japan, Western Digital makes significant investment in developing memory technology that is extremely complex. This innovation is foundational to the data infrastructure that people around the world rely on every day," said Matthew E. Massengill, chairman, Western Digital.
"Both Tom and Miyuki have strong track records of professional success and deep subject-matter expertise that will add valuable perspective to Western Digital. They will each play an influential role as members of our board and I look forward to working together.
"A demonstrated leader with over 30 years of semiconductor industry experience, Caulfield's extensive career spans roles in engineering, management and global operations. Prior to being named CEO of GLOBALFOUNDRIES in 2018, he was senior vice president and general manager of the company's 300 mm semiconductor wafer manufacturing facility (Fab 8).
Prior to that, Caulfield held senior executive positions at several leading technology companies including IBM and Novellus Systems, Inc."The semiconductor industry is core to the world's economy and is projected to double over the next eight years," said Tom Caulfield, CEO of GLOBALFOUNDARIES.
"Western Digital is the only company in the world that manufactures both hard disk drives and Flash data storage devices and is strongly positioned to take advantage of this growth opportunity. As a manufacturing executive at heart, I'm excited to join the board at this time to support the company as it navigates its growth and product strategies."
And while we are here... Lets have a little look at 3DXP...
May 06, 2021 4:36 AM ETMicron Technology, Inc. (MU)AMD, DRAM, IBM...267 Comments60 Likes |
| Summary |
| In October of 2019, Micron called Intel's share of IMFT / 3D Xpoint. |
| In March, Micron announced that they will discontinue IMFT & 3D Xpoint. |
| I believe that this is an obfuscation. Don the tinfoil hats. |
|
Photo by knowlesgallery/iStock Editorial via Getty Images |
| Last March, Micron (MU) perplexed everyone by announcing that they "will cease development of 3D XPoint™ ["3DXP"] and shift resources to focus on accelerating market introduction of CXL-enabled memory products". |
| This statement is completely nonsensical because CXL ("Compute Express Link") is agnostic of the underlying memory technology - DRAM, 3DXP, MRAM, or anything else as long as it is byte-addressable (i.e. - not NAND). 3DXP's claim to fame is its byte addressability and would therefore work fine on CXL with the appropriate controller. |
Why would Micron assume that nobody would see this conflict in their logic? I believe that this announcement is simply a clever ruse, the impetus for which may not be apparent to most investors who aren't aware of what has been happening behind the scenes. |
| Wait. What? |
| An abbreviated recap is required for those who haven't read my previous six years' worth of focus on the topic. My 2015 article "Purple Swan" predated - by a month - the hastily-prepared announcement of 3DXP by Micron and Intel (INTC). If you need more background on 3DXP, its origins, and the ongoing lawsuit surrounding it, "Purple Swan" is a good reference along with a more recent summary by Computer Business Review. |
| Just know that a Metro Detroit company known as Energy Conversion Devices ("ECD") and its founder, Stanford Ovshinsky, had been working with the technologies since the 1950s. Without explanation, ECD replaced their CEO in late 2011 in order to make a single critical decision: unnecessarily put ECD into bankruptcy and sell all of the assets - including phase change memory ("PCM"), as well as non von Neumann compute and AI - at fire sale prices. |
| This was way back in 2012. Because the technologies are so complex, it smelled funny only to a handful of ECD shareholders, including myself. Subsequently, we coordinated with the bankruptcy trust in order to reveal the true value of the assets - especially the intellectual property which now provides the basis for 3DXP. Eventually, the ECD bankruptcy brought a lawsuit to Micron, Intel, and other associated parties. |
| Deeper Dive: Micron and Intel - Fishy? |
| After many years in the court, last October, the judge issued a 146 page opinion and decided to allow the suit to proceed, kicking the close date out to June of next year with hopes that the parties can settle. At stake are damages for royalties, fraudulent transfer, and patent rights. |
| Among those patent rights are those which leverage the "phase change" and "transistor-replacement OTS" technologies for both memory as well as what we broadly know as artificial intelligence , which includes such topics that span "machine learning", "deep learning", "neuromorphic computing", "cognitive computing", "spiking neural network", "compute-in-memory", "non-von Neumann", and more. |
| I've written about the non-memory applications of PCM technology (see: Micron And Intel: The AI And Security Play Of The Century for a good example) and I believe that this will ultimately result in more value (i.e. revenue and profit) than standalone nonvolatile memory such as 3DXP and its successors. I also believe that Micron's Natural Intelligence and Intel's Loihi neuromorphic technologies are based on ECD's intellectual property. |
Deeper Dive: Intel - Beyond Today’s AI: Neuromorphic Computing |
| This would explain the many years of delay from both companies on these new technologies. It is important to note that IBM ( IBM) hasn't been shy with their progress on ECD's PCM and OTS technologies as the basis for their focus on bringing AI to a broad variety of markets. But IBM isn't implicated in the ECD suit. |
| They don't care about pursing standalone PCM because they have the vision to understand that a swath of compute and AI functions will be embedded into memory. Standalone memory - such as 3DXP - will be commoditized. Just ask the memory for answers instead of relying on transferring data to the processor (CPU, GPU, FPGA, etc.) for the requisite, expensive, and perpetually-increasing need for bandwidth. |
| Today's huge AI industry is furnished largely through GPUs from Nvidia ( NVDA) and AMD (AMD) as well as FPGAs from Xilinx (XLNX) and Altera (owned by Intel). These are all digital, von Neumann computing devices, which are characterized by the abhorred von Neumann Bottleneck that has become an ever-increasing limitation on computing power. But this will change with non von Neumann devices such as those based on PCM. |
| It is important to note that an ECD subsidiary known as Ovonic Cognitive Computer, Inc. is party to the suit, claiming rights to over 300 of the patents that were sold to Micron. |
| A Rose by any Other Name |
| In 2019, Kioxia pointed out that 3DXP isn't scalable - and they're correct. It isn't scalable in that the cost per bit decreases as more of those 3D layers are added to each chip. If you double the layers, you double the cost. Not good but not the end of the underlying PCM technology. |
| Back in 2013 when the Micron and Intel PCM patents were just beginning to pepper the patent offices, a scalable implementation of the technology was outlined, as pictured below. |
Bitmap| Source: US Patent Application 20140361239; Micron; filed June 2013 |
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Not coincidentally, Micron had just commissioned Intermolecular, Inc. in order to bring this technology to market. More recently, last August, Intermolecular announced the fruit of this R&D: |
| Intermolecular Inc., a wholly-owned subsidiary of Merck KGaA, Darmstadt, Germany, recently announced it has developed what it believes is the first quaternary atomic layer deposition ("ALD") GeAsSeTe OTS device for 3D vertical memory arrays. This device overcomes the inability to stack tens of layers in a 3D structure, which limits memory density and results in higher costs, said Intermolecular device engineer Mario Laudato. The company’s new material combination can help to realize these architectures, which would support emerging use cases such as artificial intelligence ("AI") and neuromorphic computing, and other semiconductor designs necessary for faster and more affordable digital applications. [...] |
| Intermolecular’s new approach involves the use of ALD chalcogenides in lieu of the current PVD process for 3D Xpoint, which limits film conformality and homogeneity on a large scale, he said, and as a result, precludes the integration of tens of decks in a 3D Xpoint architecture. By employing ALD chalcogenides, Intermolecular’s process enables future 3D vertical integration with higher density. |
| Intermolecular characterizes PCM as follows: |
| Phase change memory ("PCM") is a type of advanced non-volatile memory where the information is encoded in the phase (i.e. the atomic arrangement) of a material. Phase change materials are usually based on chalcogenides (they contain elements in group 16 on the periodic table, typically those below oxygen). Their atomic structure can be reversibly changed between crystalline and amorphous states by using an external electrical field or optical pulse to heat and cool the material over a specific time scale. This rapid amorphous to crystalline transition leads to change in electrical resistance up to several hundred orders of magnitude, and these low- and high-resistance states define the digital 1s and 0s of stored data. The amorphous-crystalline phase change can be triggered repeatedly with minimal electrical power in a nanosecond, so novel information storage memory built from chalcogenide materials is anticipated to out-perform some other advanced memory technologies with lower power consumption, faster switching, and higher endurance for storage class memory applications. |
| Call it what you will, here's a layout of the technology from Intermolecular's release video: |
Bitmap| Source: Intermolecular ALD Chalcogenide NVM; youtube.com |
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| Looks a lot like the oh-so-scalable 3D NAND architecture, yes? The bonus to this technology is two-fold. First, unlike 3D NAND, which has reached its 2D scaling limit and is nearing its 3D limit, the Intermolecular/Micron architecture will provide much smaller 2D cell sizes. |
| Deeper Dive: 3D NAND’s Vertical Scaling Race |
| Unlike planar NAND, which reduced the [2D] cell size at each node, 3D NAND uses a more relaxed process, somewhere between 30nm to 50nm. “Scaling in 3D NAND memory capacity is achieved in a different way: by adding vertical layers,” [...] |
| A PCM product based on a new scalable architecture will be able to reach much higher 2D densities. Therefore, fewer 3D layers will be required in order to match the bit density of 3D NAND chips. We also know that multiple bits per cell (MLC, TLC, QLC, or more) is definitely possible and probable. Here are a couple of choice quotes from related Intel patent applications: |
| MULTI-LEVEL MEMORY WITH DIRECT ACCESS |
| [0003] Phase-Change Memory and Switch (PCMS) is a non-volatile storage technology under development as a successor to the NAND non-volatile storage ubiquitous in today's solid state storage devices. PCMS offers much higher performance than NAND flash and in fact begins to approach the performance points of the Dynamic Random Access Memory (DRAM) currently used as primary dynamic storage in most client computing devices. While PCMS storage may initially be more expensive per-bit than NAND storage, that relationship is forecasted to change over time until, eventually, PCMS is less expensive than NAND. |
| AUTONOMOUS INITIALIZATION OF NON-VOLATILE RANDOM ACCESS MEMORY IN A COMPUTER SYSTEM |
| Recent versions of PCM can achieve two additional distinct states, effectively doubling memory storage capacity. PCM is one of a number of new memory technologies competing in the non-volatile role with flash memory (also referred to as "flash"). |
I am writing another article in order to expose the onslaught of memory patents that Intel has been filing. This is very uncharacteristic of them, typically leaving the memory fabrication stuff to Micron. It seems undeniable that Intel likely has plans to go-it-alone on both PCM as well as a new technology to replace DRAM. It also seems likely that they will introduce more layers into the memory system (e.g. - MRAM, CBRAM, PCM - all nonvolatile). |
| But more on that soon. Why is Intel selling their NAND business? |
| Observations |
| To me, with Micron relegating their next-gen nonvolatile memory to the CXL bus, and Intel dumping money on memory R&D, it seems probable that Micron and Intel are having more than a spat but, rather, a full-on divorce. Realize that 3DXP is just a trade name for the current implementation of ECD's PCM technologies. At this point, Micron and Intel are just burning out the expiration dates on the patents so that they can ship the fruits of ECD's labor. |
| In 2015, after Intel purchased Altera for their FPGA technology, I fully expected that Micron would move to Altera from Xilinx (XLNX) FPGAs, which comprise the basis for their Advanced Computing Group. But Micron has remained with Xilinx, which was subsequently purchased by AMD. This seems like a coordinated, amicable plan between the two given Micron's inability to front that sort of purchase as well as the mutual "enemy of my enemy" situation. |
| Micron is free to change the PCM architecture and trade name as they see fit. The current 3D XPoint™ implementation will be rearchitected as a denser, cheaper, and more capable memory. But it sounds like they're not going to be selling raw chips to Intel to use on proprietary DC Persistent Memory ("DCPMM"), as described in my article, Intel's Huge Lead in Persistent Memory. |
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| In the diagram above, the third level in the memory pool is "Intel Optane SSDs". This level is block-addressable storage - not byte-addressable memory like the DCPMM level. |
Deeper Dive: Intel Touts Optane Performance, Teases Next-gen "Crow Pass" |
| The industry is eager to replace this storage level with the open standard CXL memory interconnect, which will not only encroach into Intel's proprietary DCPMM space, but also allow other processor manufacturers to make use of persistent memory. |
| If the speed and latency of CXL is good enough, this will kill Intel's DCPMM strategy and the industry will largely collapse back to open standards, which will be good for consumers in the form of lower-than-Intel persistent memory prices for all but the most demanding applications. |
| Conclusion - It's On |
| It feels that Micron is bundling their next-gen persistent, byte-addressable memory (remember, flash is block storage - not memory) on fully-completed, direct-to-market, CXL-based products in order to add the value required to recoup their investment. It also sounds like they are cutting off Intel's supply of raw chips for use as DCPMM once their extended supply agreement expires. It is not clear whether Intel's go-it-alone memory strategy provoked Micron or vice versa. |
| Remember, as I have pointed out in a previous article, with every day, Intel DCPMM is displacing increasingly larger amounts of DRAM, Micron's current bread and butter. |
| AMD and Xilinx are going to become increasingly more important to Micron at this point. Nvidia's $40bn ARM acquisition is indicative of the looming requirement for tighter integration between the variety of compute elements at both hardware and software level, although they are attempting to forgo any dependence on FPGAs. |
| Intel has the lead with persistent memory on the DRAM bus and will maintain that lead for many years if they can obtain a supply of persistent memory that is required for their proprietary DCPMMs. Again, it Micron's announcement makes it clear that any next-gen memory will only be provided in CXL form, which Intel intends to support, albeit perhaps at the third level after DCPMM. Both Intel and Samsung (OTC:SSNLF) patent applications reveal that they are working hard on such DCPMM-capable memory technology. |
| I believe that the wildcard here is ECD and their suit - we're dead in the water until it is settled or the relevant patents dry up. Then, we'll likely see Micron's next-gen 3DXP and its newly-unleashed AI capabilities under some new name. |
| I'm predicting "QuantX". |
(20min delay)
