By the time JD is running the show around USA ALL the parameters of the wafer gonna be tested software ready for mass production by whoever buys us out. If it'll be Western Digital Corporation with offer will come a Stock Swap. For 30-50 4DS shares 1 WDC share. If that happened i'll take the Stock Swap. Here is a bit of similar FAB the testing part of it:
Main article:
Wafer testing
Once the front-end process has been completed, the semiconductor devices are subjected to a variety of electrical tests to determine if they function properly. The proportion of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields, but it can be as low as 30%.
Process variation is one among many reasons for low yield.
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The fab
tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. Currently, electronic dye marking is possible if wafer test data is logged into a central computer database and chips are "binned" (i.e. sorted into virtual bins) according to the predetermined test limits. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging.
Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test".
Usually, the fab charges for testing time, with prices in the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible, because many testers have the resources to perform most or all of the tests in parallel.
Chips are often designed with "testability features" such as
scan chains or a "
built-in self-test" to speed testing, and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during the testing, in order to achieve tightly-distributed resistance values as specified by the design.
Good designs try to test and statistically manage
corners (extremes of silicon behavior caused by a high
operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.
