Ann: 4DS Granted 31st USA Patent, page-24

Aye, and neither are the laaads over aaht John Western Digital... aka HGST B.V, Inc & technologies...

So when Guido says "the partnership with HGST has allowed 4DS to expedite the pathway to commercialisation and has meant that it hasn't had to develop gigabyte prototypes" I think I can now see what he means....

Anyone wants to know if it stacks on debut, just ask Dan the Man.... Coz if he says it does then I'd say it does :-0)

	Applicant	Inventor	Relationship	Date	Desc
1	HGST Inc		CACHE	US - 28.08.2018	14.10061775-SCALABLE AND PERSISTENT L2 ADAPTIVE REPLACEMENT CACHE
2	HGST Inc	Daniel Shepard	ECC	US - 08.03.2018	20.20180069573-INCREMENTAL ERROR DETECTION AND CORRECTION FOR MEMORIES
3	HGST Netherlands B.V		Reram	US - 28.12.2017	35.20170372781-BI-DIRECTIONAL RRAM DECODER-DRIVER
4	HGST Netherlands B.V		MRAM	US - 21.12.2017	38.20170365777-SOT MRAM CELL WITH PERPENDICULAR FREE LAYER AND ITS CROSS-POINT ARRAY REALIZATION
5	HGST Netherlands B.V		Reram	US - 09.11.2017	44.20170324033-DIFFUSED RESISTIVE MEMORY CELL WITH BURIED ACTIVE ZONE
6	HGST Netherlands B.V		Reram	US - 26.10.2017	49.20170309332-PLANAR MEMORY CELL ARCHITECTURES IN RESISTIVE MEMORY DEVICES
7	HGST Inc	Daniel Shepard	Reram	US - 21.09.2017	60.201702714073-D PLANES MEMORY DEVICE
8	HGST Netherlands B.V		ECC	US - 14.09.2017	64.20170262332-REDUNDANCY OF ERROR CORRECTION ENCODED DATA IN A STORAGE SYSTEM
9	HGST Netherlands B.V		CACHE	US - 18.05.2017	100.20170142217-SYSTEMS AND METHODS FOR ADAPTIVE PARTITIONING IN DISTRIBUTED CACHE MEMORIES
10	HGST Inc	Daniel Shepard	Reram ***	US - 11.05.2017	101.20170133435-METHOD FOR FORMING PCM AND RRAM 3-D MEMORY CELLS
11	HGST Netherlands B.V		ECC	US - 27.04.2017	104.20170116060-ERROR LOCATION POINTERS FOR NON VOLATILE MEMORY
12	HGST Netherlands B.V		ECC	US - 11.04.2017	107.09620227-CHARACTERIZING AND OPERATING A NON-VOLATILE MEMORY DEVICE
13	HGST Netherlands B.V		CACHE	US - 30.03.2017	109.20170093426-CACHE OBLIVIOUS ALGORITHM FOR BUTTERFLY CODE
14	HGST Netherlands B.V		MRAM/RERAM	US - 23.03.2017	SELF-RECOVERY MAGNETIC RANDOM ACCESS MEMORY UNIT
15	HGST Netherlands B.V		CACHE	US - 09.03.2017	114.20170068623-INVALIDATION DATA AREA FOR CACHE
16	HGST Inc	Daniel Shepard	RERAM 4F2 ***	US - 02.03.2017	120.20170062432-4F2 SCR MEMORY DEVICE
17	HGST Inc	Daniel Shepard	NVM-MASK Step	US - 01.12.2016	143.20160351627-EMBEDDED NON-VOLATILE MEMORY
18	HGST Netherlands B.V		ECC	US - 25.08.2016	159.20160246670-ERROR CORRECTION FOR NON-VOLATILE MEMORY
19	HGST Inc	Daniel Shepard	Reram ***	US - 28.07.2016	167.20160218147-METHOD FOR FORMING PCM AND RRAM 3-D MEMORY CELLS
20	HGST Netherlands B.V		CACHE	US - 21.07.2016	169.20160210232-CACHE COHERENCE PROTOCOL
21	HGST Netherlands B.V		ECC	US - 14.07.2016	170.20160203041-TRACK ERROR-CORRECTING CODE EXTENSION
22	HGST Netherlands B.V		ECC	US - 09.06.2016	175.20160162352-SYSTEMS AND METHODS FOR ADAPTIVE ERROR CORRECTIVE CODE MECHANISMS
23	HGST Netherlands B.V		CACHE	US - 14.04.2016	188.20160103765-APPARATUS, SYSTEMS, AND METHODS FOR PROVIDING A MEMORY EFFICIENT CACHE
24	HGST Inc	Daniel Shepard	Reram array***	US - 25.02.2016	204.201600562063-D PLANES MEMORY DEVICE
25	HGST Inc	Daniel Shepard	ECC	US - 21.01.2016	205.20160019112-INCREMENTAL ERROR DETECTION AND CORRECTION FOR MEMORIES
26	HGST Inc	Daniel Shepard	NVM-MASK Step	US - 21.01.2016	206.20160020253-EMBEDDED NON-VOLATILE MEMORY
27	HGST Netherlands B.V		CACHE	US - 21.01.2016	207.20160018988-IMPLEMENTING ENHANCED PERFORMANCE WITH READ BEFORE WRITE TO PHASE CHANGE MEMORY TO AVOID WRITE CANCELLATIONS
28	HGST Technologies		CACHE	US - 10.09.2015	229.20150254185-SYSTEM AND METHOD FOR CACHING VIRTUAL MACHINE DATA
29	HGST Inc	Daniel Shepard	Mem Array***	US - 04.06.2015	238.20150155033-OPERATING A RESISTIVE ARRAY
30	HGST Technologies		CACHE	US - 27.11.2014	252.20140351498-SYSTEMS AND METHODS FOR READ CACHING IN FLASH STORAGE
31	HGST Inc	Daniel Shepard	Mem Array	US - 30.10.2014	254.20140321190-VERTICAL SWITCH THREE-DIMENSIONAL MEMORY ARRAY
32	D Shep	Daniel Shepard	Mem Selector	US - 19.04.2012	282.20120096331-MULTIPLE SECTOR PARALLEL ACCESS MEMORY ARRAY WITH ERROR CORRECTION

In total over 238 HGST patents, though not all specific to 4DS... Some are just the "The Dige" de-bottlenecking a little.. hehe ;-)

	HGST Inc	Daniel Shepard	Reram ***		A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.
1	HGST Inc	Daniel Shepard	RERAM 4F2 ***		A memory-array is disclosed in which an array of threshold switching devices is constructed having an area per transistor of 2F2. This array of threshold switching devices is suitable for a variety of memory or other applications including PRAM, MRAM, RRAM, FRAM, OPT-RAM and 3-D memory.
2	HGST Inc	Daniel Shepard	Reram array***		The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for addressing the WL and BL resistance by creating arrays having not only large plane conductors for each of the memory layers (WLs) but also for the opposite polarity common layer (BL). The present invention is also a means and a method to form via interconnections between the substrate logic and the respective layers of a multidimensional array. The present invention is also a way to operate an array in which the select device is unipolar but the array is above to be operated in a bipolar way. This facilitates a bipolar operation for memory cell technologies such as Resistive RAM (e.g., RRAM, ReRAM and Memresistors).
3	HGST Inc	Daniel Shepard	Mem Array***		The present invention is a means and method for constructing and operating a 3-D array and, more particularly, a 3-D memory array. This array can be manufactured as a monolithic integrated circuit at low cost by virtue of the limited number of steps per layer of memory elements. The low number of steps results by having the storage elements separated by a resistive component as opposed to an active component. The 3-D array is in essence, an array of 2-D resistive arrays (row-planes) having a long dimension (typically along the rows) and a short dimension (typically in the direction of the stacked layers). Any one row-plane can be isolated from the rest and be accessed independently from all of the other row-planes in the 3-D array. This makes it possible to operate and analyze a single row-plane as a mostly stand-alone circuit. The present invention lends itself to single bit accesses as well as simultaneous multiple bit accesses.