4DS to kill WBT aspirations, page-73

@darrenrr
that is not correct at all
compatible with lowest geometries is correct however....

It will not scale to those material compatible geometries - etch rate fluctuations occur due to the insufficient amount of photo resist....this pushes the geometry up ...in 4DS case to 60nm to allow dry etch with hard mask
this has allowed the megabit success which is great.
Smaller geometries are not achievable at this point in time.
the performance of the cell is still being characterised at 60nm and it is a working cell at this point - not a packaged wafer ...far from it.

you will remember the “blocked etch metal island,” encountered by PL3 ...this is a direct result of the process I have described.

further
it is important to understand the behavior of these defect adders within the etching process sequence.
Among these defect adders, post hard-mask etch residue is commonly observed after the oxide hardmask patterning followed by resist ashing and wet stripping.
Such defect formation is found strongly related to the ashing process temperature as you scale the node....pretty simple to understand.

there is plenty on the web to back this up - it is not merely my opinion.

The discussions with IMEC and 4DS into a bilateral agreement to manufacture OR acquire will revolve around the potential of a 60nmfunctional cell to augment a DRAM manufacturer sufficiently in providing revenue advantage on cost per byte production in available cell area in a killer application category.

we all look forward to those discussions and the outcome.