@darrenrr@Cguvtook the time when available across the last 2 weeks to be satisfied with where things are at ...and potentially heading
Target market ....
not looking to address storage class memory ( a type of NAND that includes power source to prevent data loss)
the following as stated by W ....(much clearer now with what is known.
)
-DRAM every 60ms or so you have to rewrite data in the memory....as the charge leaks away.....and 4DS is aiming to
replace and augment DRAM .....
looking to produce chips, high speed as needed to r
eplace DRAM ' non volatile / persistent so its not a memory that will store data for 10yrs but will much longer than a DRAM...days weeks or months, as required.'
a unique position as the industry is yet to achieve speed of an SRAM and the storage capability of Nand.
current situation:
'building a wafer with just a memory stack to optimise the etch process' with a new mask to correct the design issues noted on the most recent, and the previous wafer batch.
Believe we are talking about short loop test work across the 'new'
memory stack wafer (only) to ensure yield loss correction caused primarily due to lateral dimension variation across the wafer (usually at the edge and as a result of the
chemical mechanical polishing process) and/or
lithography and etch.Lithography and etch clearly appears to be what is being talked about as the 'design issue'....( attributed to W in the presentation) these are normally systematic and dependent on the layout pattern map across the wafer....sometimes these 2 crossover / design processes flow over each other ....'process overlap'
so outcomes of these generally result in parametric and functional failure by way of many things really....dielectric erosion ...wafer 'dishing'....line end pull to contact....incomplete or eroded fin length .....many many potential offenders...
either way you are dealing with resulting 'open' circuit issues hence the yield loss.
correctable - yes
are they on it - yes
target DRAM - yes (
speed without storage as stated)
Optimising the etch and chemical mechanical polishing on the new memory stack wafer ....combined with creating a new mask to correct the design issues - remains to be seen on the results of the short loop / yield correction on that test work in Q1
back in with a small parcel till the results of that test work is revealed...or at least confirmed as successful in Q1 2022
all above seems to align with Ws' comment that 4DS are starting to make memory 'more like DRAM.....not permanent like Nand.'
I personally don't care about any tier 1, 2 or 3 ...or whatever partner......IMEC and 4DS are doing the work and if what is laid out is achieved then the commercial collateral will be the success of replacing DRAM...as stated.
back when the outcome of the test work is known....all noise till that point.
I hope for better investor relations for all concerned- remains to be seen
these are my own views and summations based on my own DD and what is known about the work to this point.
GLA
(20min delay)