AGM Questions, page-328

questions for agm.. yeah 8teys got 1 or 2

1. Is 4ds 3d memory array similar in design and suitable application to earlier vrram models developed by Samsung & Stanford, or is it perhaps better again?

And 2, would 4ds reram, assuming it has met all the 3d monolithic reram design tradeoff requirements & of course upon final verification testing, be a possible contender for next gen memory that an early adoptive major mobile company may be interested in for its 5g mobile devices..?

and finally, does the advantage of being a non volatile cmos logic compatible product mean that 4ds chip may be integrated over a cpu's last level cache in the future & what does this mean for sale prospects??

Yeah, that'll do me .... hehe

5-10 yrs from 2015 hey, well that puts things are 2025 now dont it..

Lot stuff be all happenin then it seems.. ;-)





Monolithic 3D Integration of CPU and Main Memory SystemsOverview:Certain emerging non-volatile memory technologies, such as resistive RAM (ReRAM), are compatible with standard CMOS logic processes. This means it may be possible to integrate them directly into the die of a CPU. This project investigates such monolithically integrated CPU-main memory chips. Similar to stacking DRAM dies over a logic die, monolithic 3D integration of main memory uses the vertical dimension to enable close physical proximity between main memory and compute logic. But because there are no die crossings between the cores and an on-die main memory system, much higher wiring density can be achieved, resulting in a massively parallel connection to main memory. This results in higher memory bandwidth and lower data movement.

A potentially promising approach is to integrate the ReRAM memory system over the CPU's last-level cache.

Like ReRAM, SRAM caches also consist of numerous memory arrays. It is natural to co-design the SRAM and ReRAM arrays such that one fits neatly underneath the other. For example, a 3D memory building block is illustrated below in which a cache mat consisting of two SRAM sub-arrays is physically integrated underneath two ReRAM sub-arrays. Routing of the address and data busses into and out of the co-designed arrays is still required, so layout of the ReRAM peripheral access circuitry needs to accommodate those routing tracks. But the resulting routing congestion is considerably less than what would be incurred if the ReRAM is integrated over random logic.Architecture ResearchOne of the research goals is to develop a CPU architecture that can make use of the massive memory-level parallelism afforded by monolithically integrated main memory systems. Currently, a large tiled CPU (illustrated below) is being considered. To exploit the memory-level parallelism capabilities of the on-die ReRAM, the tiled CPU is equipped with multithreaded cores plication's data can be partitioned across the main memory modules such that the cores' memory accesses are destined primarily to the local portion of main memory.Circuits and Devices ResearchCurrent commercial ReRAM technology is targeted for storage applications. An important research direction is to re-target the technology so that it is better suited for CPU main memory. One approach under consideration is to tradeoff retention, normally an important characteristic for non-volatile memories, in order to improve other characteristics which are crucial for CPU main memory, such as latency, energy and endurance. While storage devices require high retention, CPU main memory does not.