AKP Chart Thread, page-67

Here's what I think. Our company is investing in the tools and expertise to be able to maximise its IP's potential applicability. While I do not fully understand the details of the tech or the range of FPGA's applicability to our MEMS, clearly Danny Lewin and his associates at AP do. And they are on the case even as we speak. There will undoubtedly be new products and applications under development in the future. That gives me confidence and optimism in spade fulls!

I recall that tuning the pixels with the array was mentioned as being something that could and had to be done. I have interpreted that as meaning they could adjust the timing of actuation of each pixel element individually to ensure that they were all able to be choreographed to actuate in synch. Not just to trigger at the same time, but to move in physical reality at precisely the right time. This would be something that was done at the time the chip's performance was being initialised. The adjustments were presumably written to the ASIC's memory.

They also talked about turning off any pixels that were dead or faulty so they could be bypassed in the actuation algorithms. That would also be the kind of data that was written to the ASIC at initialisation.

But I believe they also mentioned being able to monitor the chip as a whole during its lifetime whenever it was turned on, and if any pixels faulted, of being able to turn them off and reconfigure the array to work without them.

I am assuming that all of these functions are provided by FPGA. But I stress that this is only my take on the situation. I could be completely wrong. Danny may be able to tell us more if the company wants us to know more of the details. As I have said elsewhere: ask the chicken why he crossed the road.