Ann: 12CQ chip development progress update, page-35

A few more details worth highlighting -

Image 2. An Archer 4 x 4 mm single-chip quantum electronic device after installing and bonding
into a commercial chip carrier. This completed device is compatible with measurement setups
for electronic characterisation at cryogenic temperatures as well as ambient conditions at room
temperature using Archer’s in-house lab capabilities as well as external facilities


What I see is that they plan to test at least a 150 QEDs with the individually prepared qubit material. Testing in different conditions and operating environments. The electronic characterisation of the chip to work at room temperature will be different to the one needed to operate in cryogenic conditions. We shouldn't be surprised if after finishing this test they then test at high temperatures. Real world applications also include reasonably hot spaces. If this chip can find a place in cars, it definitely needs to work outside room temp. And then what about fridges, cold rooms. And what does ambient temperature mean all over the world, it varies widely. And what about in defence applications. Now of course some of these variances in environment can be dealt with by using an inert vacuum. Hence they're going to introduce one into some of the chips. This is a no stone left unturned approach to testing in every possible environment and quite thorough.



...These QEDs integrating qubit material have allowed for ongoing
testing and measurements that aim to validate quantum electronic properties that could
potentially be exploited towards qubit readout approaches

....While the Company’s technology remains focused on quantum
devices that can operate at room-temperature, the cryogenic measurements are necessary to
advance development of qubit readout and control mechanisms in Archer’s chip-based quantum
logic devices


And below we see the company's approach is multi wafer and multi project. Not only different operting environments, but different nm chip fabrication processes.

...Archer staff, working at a Sydney-based prototyping semiconductor foundry have recently
developed a multi-scale wafer fabrication process for its quantum electronic devices


.....This permits Archer to access TSMC semiconductor fabrication process technologies, which include the most
advanced technologies and also more mature process technologies (e.g. 180 nm and 130 nm
processes). This will allow Archer to perform cost-effective multi-project wafer runs, and
potential tape out and industrial production of future devices. Contractual relationships with
TSMC will be on a case by case basis.

Doing a wafer run at a fab requires advance planning to get the most out of an expensive process. AXE is certainly planning meticulously to make it as cost effective as possible. Looks like they plan to do several wafer runs at 180nm, 130nm , which are standard semiconductor chips and also the more advanced smaller nm sizes and who knows how low. TSMC started 3nm in 2022.

multi scale wafer, multi project means different sized quantum electronic devices for different applications. Let's see what the next bulletin says.