I sent the below questions to Eric.Q1. In January, Weebit and...

I sent the below questions to Eric.

Q1. In January, Weebit and Silvaco partnered to develop a Technology Computer-Aided Design (TCAD) solution to accurately model the electrical behaviour of Weebit’s ReRAM devices. What is an estimate for when the TCAD solution will be completed and potential partners can start using this software?

Q2. For the most recent patents optimizing ReRAM performance, can you please explain what they mean, e.g. what "electrical performance" means?

Q3 With the work from the letter of intent signed by Weebit and XTX Technology, would it require the Silvaco TCAD solution or the Korean partner “proof of concept” module to be completed before it could start?

Q4. Weebit has made significant progress in terms of improving the technical parameters. In regards to the work that is ongoing for other improvements:
- Is it always going to be ongoing and driven by customer demand or do we expect to reach a point where all the standard memory performance characteristics for the 40nm or 28nm chips, e.g. read and write speeds, heat dissipation etc. will be good enough to be published.
- Once we reach 28nm and the work Leti is doing with us is reduced or stopped, will there be an impact on Weebit's ability to complete these performance optimizations?

Q5 What happens with the Leti relationship after the 28nm could there be a possibility of working on other neuromorphic computing projects or anything else?

Q6. Is it possible to share a breakdown of the timeline for the work on the customer module, so that we can better understand the work required and why it will take until mid next year to complete?

Q7 Has Leti or Weebit done any exploratory work to explore the stacking of layers to increase density?

Q8. How complex is the in-memory processing capability, i.e. is it simple adds or more complex functions? Does the additional logic needed reduce the amount of storage cells available on the chip?

Q9. Does Weebit have any plans to increase the amount of memory per chip? If so, what would that be, e.g. 4MB or 16MB, or would the plan be to just increase the number of chips on a wafer, i.e. add more 1MB chips?

Q10. Does Weebit expect any potential issues with getting fab time at 300mm and if there are potential issues is 28nm on 200mm a possibility?



@jsbuser I didn't add Q3 and Q4 as I believe they were answered in Eric's previous response and Q10 because it will depend on how much is raised in the entitlement offer and I expect the standard response that Weebit is an early stage company which means that other cash raises might be required.