I received a response from Eric this morning. His responses are...

I received a response from Eric this morning. His responses are in red.

Q1. In January, Weebit and Silvaco partnered to develop a Technology Computer-Aided Design (TCAD) solution to accurately model the electrical behaviour of Weebit’s ReRAM devices. What is an estimate for when the TCAD solution will be completed and potential partners can start using this software?

Weebit and Silvaco are on track co-developing the TCAD module. The project duration is approximately one year.

Q2. For the most recent patents optimizing ReRAM performance, can you please explain what they mean, e.g. what "electrical performance" means?

Electrical performance means the device behaviour in a product and the importance of these patents are the ability of the device to meet the specified requirements over time.

Q3 With the work from the letter of intent signed by Weebit and XTX Technology, would it require the Silvaco TCAD solution or the Korean partner “proof of concept” module to be completed before it could start?

Work with XTX has already started. We shipped them a packaged array which they are analysing now, and we kicked off the joint exploration of how we can collaborate. This is not dependent on Silvaco or the module we are developing and is going on in parallel to that work.

Q4. Weebit has made significant progress in terms of improving the technical parameters. In regards to the work that is ongoing for other improvements:
- Is it always going to be ongoing and driven by customer demand or do we expect to reach a point where all the standard memory performance characteristics for the 40nm or 28nm chips, e.g. read and write speeds, heat dissipation etc. will be good enough to be published.

In the semiconductor domain you never stop improving. If you are not making forward progress you are actually falling behind. We will be both continuing to improve the base technology as well as adapting it to new fabs, and also to the constant changes in the fabs.

- Once we reach 28nm and the work Leti is doing with us is reduced or stopped, will there be an impact on Weebit's ability to complete these performance optimizations?

We plan to keep working with Leti in the long run, constantly looking for ways to improve the technology.

Q5 What happens with the Leti relationship after the 28nm could there be a possibility of working on other neuromorphic computing projects or anything else?

Leti is a close partner and we plan to keep working closely with them in different domains, including technology improvement and neuromorphic, and potentially expand to even other related domains.

Q6. Is it possible to share a breakdown of the timeline for the work on the customer module, so that we can better understand the work required and why it will take until mid next year to complete?

The work depends on many parameters which are hard to predict. There are also different ways to address many of the tasks and we will decide which way to go as we progress. Weebit is more transparent than most public companies in the detailed plans it provides and we think going into any more detail will have negative effects on the company (from a competition point of view).

Q7 Has Leti or Weebit done any exploratory work to explore the stacking of layers to increase density?

This is a big project. We have started discussions on initial ideas around this concept.

Q8. How complex is the in-memory processing capability, i.e. is it simple adds or more complex functions? Does the additional logic needed reduce the amount of storage cells available on the chip?

There is some confusion in the market in what people call in-memory-compute. Some people refer to simply adding some logic into the memory module alongside the array. This is not a major issue and is very project dependent. It doesn’t lower the size of the array required and just moves the location of the logic allowing more efficient communication between the processor and the memory. The second type is what the Technion calls “Real Processing-In-Memory” where the memory cells themselves are wired in special ways to perform logic operations. This is still very academic.

Q9. Does Weebit have any plans to increase the amount of memory per chip? If so, what would that be, e.g. 4MB or 16MB, or would the plan be to just increase the number of chips on a wafer, i.e. add more 1MB chips?

Currently we already have large enough arrays to address the vast majority of the needs in embedded designs. We are focused on moving to production with this and getting initial orders. However, we have very clear plans to continue to grow the array sizes and have several ideas on how to do this efficiently.

Q10. Does Weebit expect any potential issues with getting fab time at 300mm and if there are potential issues is 28nm on 200mm a possibility?

Weebit has focused development at 200mm given the cost and availability were much more favourable. Given every minute on a fabrication line is very expensive, it is never easy to secure time. However, we believe that we are talking with the right partners and fabricators to ensure we can transfer our technology to production in line with our timelines.