Ann: 2019 Annual General Meeting - Update to Details, page-4

Thanks smulv, I'll start:
1. When will we see standard memory performance characteristics published for the 40nm chips ie read and write speeds, heat dissipation etc.
2. Why, if Leti could package working chips quickly after 1st silicon will it take so long for the interfacing to the SK potential customer's technology? What are we doing that is so special in this regard?
3. Why didnt we seek a joint development with the SK potential customer instead of doing the packaging work to their requirements for free? Surely the SK potential customer sees merit in exploring the technology, so isnt this a big risk to the company, doing work without joint skin in the game?
4. Is there a contract with defined acceptance criteria for the work and follow on steps we are doing with the SK potential customer or is it hope and pray?
5. With the SK potential partner now involved, how does this affect the Leti relationship?
6. Has Leti done any exploratory work yet to explore the stacking of layers to increase density?
7. How complex is the in-memory processing capability ie simple adds or more complux functions? Does the additional logic needed reduce the amount of storage cells available on the chip?
8. For 28nm, is the intent to increase the amount of memory per chip? If so, what would that be 4MB, 16MB or is the intent to just increase the number of chips off a wafer, ie more 1MB chips?
9. Is 28nm on 200mm a possibility if getting fab time at 300mm is an issue?
10. Next cap raising projected for when, or will we have a revenue stream by then?

Happy for these to be improved on and again thanks.
Cheers