I didn't expect a sale until after the completion of PLs 5 and 6...

I didn't expect a sale until after the completion of PLs 5 and 6 anyway.

But let's be honest - this is a significant capability pivot - it is much more far reaching in scope and application than what they indicated in the past. And all at 60 nm - who cares about the node size if the capability is novel?

None of the upcoming platform lots are about getting 4DS RERAM to function as analogue memory or within a analogue processor. The end goal of PL6 is to demonstrate they can fab the megabit test array at 20 nm,

That means - more development lots - now, whether those occur under the stewardship of the current team, or under the development arm of a buyer - is anyone's guess.