I think everyone needs to remember that, even if this platform lot cannot function as standalone megabit memory, it still can be operated as megabit memory - the remaining components should be operable from the test rig. The important thing is that the arrays on the platforms are switchable - which we know that they are. Metrics can still be assessed - they may not be quite as snappy as having the control logic native to the platform - but these guys will know kind of performance gains are possible by embedding the control logic on the chip.
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I think everyone needs to remember that, even if this platform...
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