Ann: 4DS Technical Update, page-183

hey Unc... Check these guys out for ref:











Order of magnitude anyone??


17 August 20214DS TECHNICAL UPDATE • New process breakthroughs have made 4DS’ Interface Switching ReRAM technology fully compatiblewith state-of-the-art high-volume DRAM and NAND production processes


As for new processes and selectors there are a couple of options...

"4DS has for the first time demonstrated fabrication of fully crystalline Pr1-xCaxMnO3 (“PCMO”) at temperatures compatible with the advanced processes run in today’s leading-edge high-volume memory DRAM and NANDfactories;"


It aint fact, but I'm willing to speculate that the boys got something going on and "the Dige" wants in ASAP.

HGST (Western Digital) Technical Update
"Clause 2.2(h) of the 2014 HGST Joint Development Agreement (JDA) requires 4DS to share all technical results with HGST, a 100% subsidiary of Western Digital. HGST have requested a detailed review of the results from these two wafer lots and this meeting is expected to occur as soon as possible"

Not sure i'd want top be sitting on the sidelines waiting too long now..... Just sayin

Recent progress in the field of 3D vertical ReRAM (V-RRAM)
There are two main reasons why V-RRAM seems an inevitable technology for future 3D SCM. First, it
promises a more cost-effective way to fabricate high density 3D SCM than H-RRAM, as every stacked
layer of H-RRAM requires additional lithography mask. Second, a similar technological infrastructure
for the V-NAND already exists [9] and being utilized for the production of high-end flash memories. At
this stage the V-RRAM is in a less matured stage than H-RRAM due to technologically more challenging
vertical design (Figure 4(c)) employing self-selecting cells. The thickness of all the layers forming the
vertical ReRAM cell has to be precisely controlled, not to increase total area footprint on the chip [67].
3D deposition conformity is the key, as the thickness control has to be maintained in all X, Y and
Z directions to minimize the cell-to-cell and layer-to-layer variability. So far, ALD is the only massproduction compatible deposition technique to offer this kind of tight deposition process control [64].
However, compared to physical vapor deposition (PVD) techniques, stoichiometry control and defect
engineering—so essential for ReRAM, are more challenging with ALD due to its very nature of nearstoichiometric deposition. Self-rectifying ReRAM cells, which provide sufficient NL to suppress the sneak
currents without the need for an additional selector, are necessary for the vertical cell design. It seems
that the utilization of the interface-limited (area dependent) RS mechanisms—often non-filamentary, can
provide for such a non-linear characteristics, as shown later. In this chapter, we review the work on
ReRAM cell designs suitable for V-RRAM utilizing filamentary as well as non-filamentary mechanisms.

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