In the “DEVELOPING NANO SCALE CELLS FOR STORAGE CLASS MEMORY”...

In the “DEVELOPING NANO SCALE CELLS FOR STORAGE CLASS MEMORY” announcement, 20th October 2016

Why is 40nm significant?
The biggest technical barrier for manufacturers of storage class memory is size
• Memory technology developers are in a race to achieve a resolution of 40nm• Ability to scale down to 40nm is essential for mass market adoption of storage class memory
• Demonstrating the potential for ongoing scalability is critical for a memory technology to be viable
• 40nm is below the current size of conventional 3D Flash memory of between 45nm to 50nm• The Flash market is estimated to be around US$40 billion
• 40nm represents the target cell size needed to prove the value of 4DS’ technology to memory makers

In the “ 4DS TECHNICAL UPDATE” 2021.

Second Platform Lot wafers demonstrated both device-scaling to imec’s minimum geometry and memory switching with an access device on 300mm wafers using state-of-the-art production equipment

From imec website.
https://www.imec-int.com/en/infrastructure

300mm cleanroomDelivering world-leading R&D on the next-generation technology nodes with our global partners.All necessary 300mm equipment to allow advanced sub-7nm CMOS R&D.