Ann: 4DS Technical Update, page-388

Right o.... Lets pluck this chicken..

None of the issues reported on the 4th of November were highlighted as being required when the company carried out extensive testing in the 17th of August update from the platform lots completed in April & where they advised extensive analysis of both the 2nd platform lot and 3rd non platform lot had been conducted...

17 August 2021

4DS TECHNICAL UPDATE

• New process breakthroughs have made 4DS’ Interface Switching ReRAM technology fully compatible with state-of-the-art high-volume DRAM and NAND production processes

• Third Non-Platform Lot wafers yielded an order of magnitude decrease in cell on-resistance, which translates into an up to one order of magnitude boost in read speed

• Second Platform Lot wafers demonstrated both device-scaling to imec’s minimum geometry and memory switching with an access device on 300mm wafers using state-of-the-art production equipment

• Third Platform Lot utilizing imec’s megabit memory platform is planned to start late Q3 2021

• HGST (100% subsidiary of Western Digital Inc) requests technical update to share the detailed results of these two lots 4DS Memory Limited

(ASX:4DS) (4DS) (the Company), is pleased to advise the results of extensive analysis of the Third Non-Platform and the Second Platform Lot wafers.

The backgoround of which has been to assess the parameters for storage class memory.

Background to Non-Platform Lots to date Since 2020 the focus of Non-Platform Lots has been to fine tune and optimize the process parameters of 4DS’ memory cell technology for StorageClass Memory. Over the past twelve months 4DS has completed two Non Platform fabrication runs on imec’s state-of the-art production equipment and results of these are set out below.

In April 2021 4DS commenced the production of a Third Non-Platform Lot and after extensiveanalysisthe Company now provides a technical update on the Third Non-Platform Lot.

Results of Third Non-Platform Lot (No mention of any issue of any kind in the 3rd non platform lot)

In this Third Non-Platform Lot, the Company continued to tune the parameters of its Interface Switching ReRAM technology to achieve compatibility with state-of-the-art processes currently used in high volume memory production. Analysis of the wafer results has confirmed that

− 4DS has been able to repeat the results for each of the key memory characteristics (speed, endurance, and retention) that were achieved with the Second Non-Platform Lot (1 February 2021 announcement”);

− All 23 device wafers in the lot were functional;

− 4DS has for the first time demonstrated fabrication of fully crystalline Pr1-xCaxMnO3 (“PCMO”) at temperatures compatible with the advanced processes run in today’s leading-edge high-volume memory DRAM and NAND factories;

− 4DS has demonstrated that this fully crystalline PCMO material reduces the cell on-resistance by an order of magnitude compared to the PCMO material fabricated in the Second Non-Platform Lot. This reduction in cell on-resistance directly translates into a significant improvement in read speed; and

− This significant performance improvement also means that full characterization (speed, endurance, retention) of memory cells with this fully crystalline PCMO material requires memory cells operating in a memory array where currents are controlled and limited by access devices.

Dr Guido Arnout, Chief Executive Officer and Managing Director commented “This important milestone in 4DS’ technology development pathway allows us now to focus on doing the same for integration of our ReRAM technology into imec’s megabit memory platform”.

Background to Platform Lots to date

Initial Platform Lot

The 24th June 2020 announcement stated that the information gathered from testing the Initial Platform Lot enabled 4DS to identify which process steps required further tuning, to benefit future platform iterations.

The 1st February 2021 announcement stated that the positive learnings from the Second Non-Platform Lot would be incorporated into the process conditions for the Second Platform Lot.

Results of Second Platform Lot

A technical issue during the fabrication of the Second Platform Lot at imec affected all wafers and most test structures on each wafer. Thistechnical issue has quickly been identified during detailed analysis and isresolvable going forward with no delays to current timelines as detailed below. Significantly, despite this technical issue, the Second Platform Lot still yielded some critically important results:

− The Company has for the first time demonstrated scalability of its memory cell to the smallest cell geometries supported on imec’s memory platform on 300mm wafers using state-of-the-art process equipment; and

− The Company has also for the first time demonstrated memory cell switching using an access device which is a critical step for producing a functional megabit memory array.

Drs. Wilbert van den Hoek, Non-Executive Chairman stated “4DS Memory has made significant and industry recognisable progress since my appointment as Chairman in November 2020.The Third Platform Lot production run moves the Company closer to demonstrating its ReRAM technology in a functional megabit memory macro. On behalf of the board of 4DS, I would like to personally thank 4DS’ management and our industry partners, who have under difficult COVID-19 conditions delivered important technical achievements in a timely fashion and within budget”.

The results of the analysis of the Second Platform Lot andthe Third Non-Platform Lot bring 4DS and its partners closer to realizing theirstrategic objective of commercialising the Company’s technology.

All is sweet and then after a 4 week hiatus we get this shite...

4 November 2021

4DS TECHNICAL UPDATE

• Extensive additional testing of Third Non-Platform Lot wafers with up to one order of magnitude boost in read speed has identified a potentially modest degradation in endurance

• A Third Platform Lot memory stack etch mask modification is needed and further optimization of the etch process utilizing this new mask will be required before the Third Platform Lot can be started

• After successful completion of the memory stack etch optimization, a Third Platform Lot utilizing imec’s megabit memory platform will be started.

• 4DS and imec have negotiated a one year extension to their Collaboration agreement


And WTF is this knackers about no SCM market and pray tell the relevance, let alone the ignorance of the statement!! Somebody Please?

Background to Non-Platform Lots to date

Since 2020, the focus of the Non-Platform Lots has been to fine tune and optimize the process parameters of 4DS’ memory cell technology for Storage Class Memory and on 17 August 2021 the Company released a summary of the results for all three Non-Platform Lots.

As announced on 17 August 2021, 4DS demonstrated that fully crystalline PCMO material reduced the cell on[1]resistance by an order of magnitude compared to the PCMO material fabricated in the Second Non-Platform Lot.

Of course there is a storage class memory market....

Storage Class Memory

As there is no established market for Storage Class Memory, the Company continues to explore speed, endurance and retention performance and are quantifying the trade-offs between these parameters. Fully quantifying the tradeoffs between these parameters will enable our future users to select the operating space which is most attractive for their future applications that require memory solutions “between” DRAM and NAND.

Updated Analysis following additional testing

Since 17 August 2021, 4DS has continued to improve its test capability to extract additional information from the Third Non-Platform Lot on endurance of its memory cells. Improvement in the Company’s test capability has shown that while endurance of these improved cells remains several orders of magnitude better than NAND endurance, it has potentially degraded when compared to the Second Non-Platform Lot performance reported in a Company announcement on 1 February 2021. Part of this degradation may be caused by test related issues resulting from testing the memory cell without an access device.

These testing challenges highlight the need to switch from using Non-Platform Lots to using Platform Lots which include imec access transistors. The Third Platform Lot will also include a test chip: an imec 1 megabit array using 4DS’ ReRAM cells.

4DS expects that the results from the Third Platform Lots will resolve the ambiguity of the endurance test results to date.

From August 2021.... There was no ambiguity!!! Except for the fact the company wants to go nano tech perhaps..

Results of Third Non-Platform Lot

In this Third Non-Platform Lot, the Company continued to tune the parameters of its Interface Switching ReRAM technology to achieve compatibility with state-of-the-art processes currently used in high volume memory production. Analysis of the wafer results has confirmed that

− 4DS has been able to repeat the results for each of the key memory characteristics (speed, endurance, and retention) that were achieved with the Second Non-Platform Lot (1 February 2021 announcement”);

− All 23 device wafers in the lot were functional;

State of the Art is currently FinFET at 3nm we know this from Imecs roadmap... So where to next... Nanosheet of course.

Which ties in with both imecs vision and that of Stanfords Nanotech research department

imec production of a Third Platform Lot with imec access transistors

imec Non-Platform Lots only support standalone 4DS ReRAM memory cells whilst the Third Platform Lot will include 4DS ReRAM memory cells with imec access transistors. This will enable more precise measurements of endurance and retention at the higher currents that resulted from the process improvements made in the Third Non-Platform Lot.

Following further testing of the Second Platform Lot the Company and imec have engaged in extensive discussions on technical matters regarding these results and the successful manufacture of the Third Platform Lot, which was announced in the 17 August 2021 press release. The additional testing results and the above referenced technical matters are the reason the Company sought a trading halt on 8 October 2021. Subsequently the Company entered into a voluntary trading suspension. The Company has been working very closely with imec to ensure that the Third

Platform Lot will deliver the desired technical outcomes.

4DS and imec have now concluded these discussions. The start of the Third Platform Lot is now expected to occur in early 2022 and will be preceded by a memory stack etch mask change and further etch process optimization to resolve the technical issues that resulted in the partial failure of the Second Platform Lot as announced on 17 August 2021. Performing this memory stack etch optimization will result in a three month delay of our time line.

Following the successful completion of this work, the Third Platform Lot utilizing imec’s megabit memory platform will be started. The expected out-of-fab date is July 2022. Because the processing of the Third Platform Lot will occur in the first half of 2022, the Company has negotiated a one year extension of the current agreement with imec, which was scheduled to expire by 31 December 2021.



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And look I'm happy with where I believe they are headed but as Clint Eastwood once said "Don't p*** down my back and tell me it's raining" on a 3 month delay with that BS announcement release do you understand....

Good!

8tey, out...