Ann: 4DS Technical Update, page-286

Hospital? hope all is good.

pre imec engagement, Western Digital played a pivotal role through the JDA to validate 4DS technology and scale it’s memory cell to 40nm.




During the imec engagement, Western Digital did step in at one point to provide input which resulted in the Additional Wafer (platform) Lots that resulted in the below.



Since then Western Digital have returned back to stealth mode. I believe not many people outside of this forum would even know that Western Digital has a JDA with 4DS Memory.

Dr WvdH mentioned that Western Digital did provide 4DS a set of parameters that they would like to see and I suspect that 4DS have nailed the hell out of those parameters when they used the term “exceeded storage class memory requirements”. Dr WvdH did also mention that post imec, our technology will end up at Stanfords 300mm Nanofabrication facility to continue with optimising 4DS technology, however believe Western Digital will want to expand on the current JDA and take 4DS technology to its KIOXIA fabs in Japan to qualify it before making a take over offer.

Question is now that we have highly experienced industry folks like Dr WvdH and Ken H running the show, Western Digital may have to be very convincing to win them over.

The upcoming JDA may be very different.