Taken...

Taken from:
https://anysilicon.com/verification-validation-testing-asicsoc-designs-differences/

SoC Validation is a process in which the manufactured design (chip) is tested for all functional correctness in a lab setup. This is done using the real chip assembled on a test board or a reference board along with all other components part of the system for which the chip was designed for. The goal is to validate all use cases of the chip that a customer might eventually have in a true deployment and to qualify the design for all these usage models. Validation happens initially for individual features and interfaces of the chip and then can also involve running real software/applications that stress tests all the features of the design. Validation team usually consists of both hardware and software engineers as the overall process involves validating the chip in a system level environment with real software running on the hardware.

There are some companies that use the term Validation in a broader perspective and classifies the activities before and after Silicon/chip availability. Verification hence is also referred to as Pre-Silicon Validation (indicating activities before the silicon chip is available) and Validation is also known as Post-Silicon Validation.

SoC Testing (Manufacturing/Production test) involves screening manufactured chips for faults or random defects, reliability, functional defects and electrical characterization before volume shipment.

The first level of testing happens on a wafer level before individual dies are packaged. This is known as Wafer sort/probe testing that characterizes the various technology and transistor parameters before the die is cut out. This step helps in identifying faulty dies before packaging.

The next level of testing happens on a packaged die to stress for reliability by testing at increased temperatures and identifying chips that can fail easily. This process is known as burn-in stress testing.

The third level of testing is used to identify manufacturing defects or faults. At a high level this process involves stimulating the input ports with various test patterns (also known as test vectors) and comparing the output responses against expected results. Tester equipments like ATE (Automatic Test Equipment) are used which can take individual chips and run IC testing, with test pattern stimulus and response checked automatically.

The next level of testing is to characterize and screen chips before volume shipments. Characterization involves testing the design with voltage and frequency shmooing to find the ideal operating conditions. Designs with high speed IOs (like PCIE, Ethernet, DDR etc) also goes through characterization of IO ports by shmooing various electrical parameters to arrive at ideal transmission and error rates.

Functional defects are identified in the parts using functional test patterns. These functional test patterns are identified to exercise the different parts in a chip to achieve satisfactory coverage and run at actual speeds.

MY TAKEAWAY:
Validation is more important than testing in our situation. I trust in Socionext and TSMC to have the manufacturing down pat. They have a proven track record and are among the best in the world at what they do. So yes, validation news is BIG in my opinion. Please correct me if I'm wrong.