Touche I missed the date however the following quick google search makes it clear that the updated system is not "functional testing" but simply checking that the structure of the chip is correct after which functional testing and bench marking occurs.
Secondly it makes clear that the rapid advances in chip technology is constantly creating obsolescence in the DFT which need to be constantly updated so a 2017 testing system will no longer be state of the art and the results related thereto for 2017 technology have no relevance to testing in 2020 on a chip as revolutionary as the AKIDA1000.
So if you do in fact hold perhaps you might change your details as even in the post which states you hold 200,000 shares you are stating you do not hold.
So again I ask you for support of your statements that three weeks is a long time and that it indicates a problem.
"Most tool-supported DFT practiced in the industry today, at least for digital circuits, is predicated on aStructural testparadigm. Structural test makes no direct attempt to determine if the overall functionality of the circuit is correct. Instead, it tries to make sure that the circuit has been assembled correctly from some low-level building blocks as specified in a structuralnetlist. For example, are all specifiedlogic gatespresent, operating correctly, and connected correctly? The stipulation is that if the netlist is correct, and structural testing has confirmed the correct assembly of the circuit elements, then the circuit should be functioning correctly.
Note that this is very different from functional testing, which attempts to validate that the circuit under test functions according to its functional specification. This is closely related to functional verification problem of determining if the circuit specified by the netlist meets the functional specifications, assuming it is built correctly.
One benefit of the Structural paradigm is that test generation can focus on testing a limited number of relatively simple circuit elements rather than having to deal with an exponentially exploding multiplicity of functionalstatesand state transitions. While the task of testing a single logic gate at a time sounds simple, there is an obstacle to overcome. For today's highly complex designs, most gates are deeply embedded whereas the test equipment is only connected to the primaryInput/outputs(I/Os) and/or some physical test points. The embedded gates, hence, must be manipulated through intervening layers of logic. If the intervening logic contains state elements, then the issue of an exponentially explodingstate spaceand state transition sequencing creates anunsolvable problemfor test generation. To simplify test generation, DFT addresses the accessibility problem by removing the need for complicated state transition sequences when trying to control and/or observe what's happening at some internal circuit element. Depending on the DFT choices made during circuit design/implementation, the generation of Structural tests for complex logic circuits can be more or lessautomatedor self-automated[2][1]. One key objective of DFT methodologies, hence, is to allow designers to make trade-offs between the amount and type of DFT and the cost/benefit (time, effort, quality) of the test generation task.
Another benefit is to diagnose a circuit in case any problem emerges in the future. Its like adding some features or provisions in the design so that device can be tested in case of any fault during its use.
Looking forward[edit]
One challenge for the industry is keeping up with the rapid advances in chip technology (I/O count/size/placement/spacing, I/O speed, internal circuit count/speed/power, thermal control, etc.) without being forced to continually upgrade the test equipment. Modern DFT techniques, hence, have to offer options that allow next generation chips and assemblies to be tested on existing test equipment and/or reduce the requirements/cost for new test equipment. As a result, DFT techniques are continually being updated, such as incorporation of compression, in order to make sure that tester application times stay within certain bounds dictated by the cost target for the products under test."
(20min delay)