Gluten you're a smart cookie, or should I say a gluten-free cookie. Re. Point 1 - the scenarios I've run through mentally during my evening walks are:
a) The IP Block is too expensive - can't really comment much on this without more info. Under the Price & Availability section of the Linley report it's stated "BrainChip withheld pricing", which is not necessarily ominous, given we know the chip is cheap as chips.
b) The execution engine isn't good enough - I've concluded this can't be the case after reading the Linley Report, which praises Akida's functionality and versatility, and given that Linley are Mike Demler are trusted authorities.
c) The APIs are inflexible - A good system needs good APIs if you want to integrate it with other systems; and the company has stated the execution engine is "Easily accessed through API calls in a Python script, (allowing users to) specify their neural network topologies, training method, and datasets for execution"... so I don't think there's an issue here. Demler would probably have pointed it out too, if there were inadequacies with the APIs
d) Companies have shown interest, but it takes TIME for the ip-block to be designed into a phone, for instance. And given the outcome of previous mentions of design-wins, the company are remaining tight-lipped this time.
This article (from chip manufacturer Sivers IMA, who designs RF chips and antennaes) talks about the development cycle of physical chips:
> First, a prospective company will sample (hence the "available for sampling" BRN have mentioned) the chips, which leads to design wins
> A design win means a customer has signed a contract and has decided to develop a product based on our technology
> The number of design wins with the right customers are one of the most decisive factor for the total outcome
> On the whole,
new products...
will start generating volume product
revenue for a hardware company like Sivers IMA,
after three to four yearsThe article also looks at Sivers' hardware development cycle - I'm assuming Phase 1 can be ruled out with our IP-block, so we can start roughly at Stage 2 when somebody shows interest:
- Prototype development phase(8-14 months):Productspecification, system partitioning,design, layoutand fabricationofthe prototypechip (or break-outs to test different blocks before you make a full chip). The time is of course dependent on the complexity of the chip and the foundry used for fabrication of chips etc.
- Test and verificationand pre-qualificationphase (3-5 months): Customer testing of prototypes to find issues and bugs and qualification of products.
- Final product development phase(6-10 months): Redesign and fixing issues and bugs, fabricationofthe “finalchip”.
- Re-test and verificationphase and finalqualificationphase (3-4 months):Final verification and final product qualification.
Total cycle:Approximately 2-3 years Minus 8-14 months if we rule out Stage 1. Or at least that what I'm concluding, for now, as I think about the IP-blocks during my walks.
(20min delay)