Dont you guys re-read older announcements?
Packaging the dies into a chip has a significant number of problems that have to be resolved. We know this. AKP knows this. They went through it when they had the packager go through it in Germany some time back. They resolved it all then. That is how they know how difficult it is. I have held one of the packaged chips in my hand and had a close look at it, so I get the problem. Check the story out below. It is totally consistent.
AR - 8/3/21
"... Demonstration Capabilities ‐ During the reporting period the company expended considerable resources designing and building electronic circuitry that enable the company to demonstrate and showcase the capabilities of our technologies. This effort also included developments associated with the packaging of individual chip as well as chiparrays (multichip demonstration). Effort in this regard including the qualification and addition [of an] assembly and packaging vendor, located locally in order to help overcome logistical complexities spurred by the COVID pandemic experienced by our European based vendors and their global suppliers.
NB my text[changes] that make better sense of the commentary I believe.
While a number of technical issues arose during the reporting period, solutions have been identified and successfully implemented to resolve all known challenges. Overall, the magnitude of accomplishments achieved during the reporting period present a positive outlook on the company’s ability to reach in a timely manner, its next critical milestone involving demonstrating our technology to the marketplace. ..."
Announcement 8/3/21
"... We refer to our prior announcement of 1 February 2021, whereby the company advised that its packaging vendor anticipated shipment of packaged chips by late February. Due predominantly to logistical complications, the vendor has since revised its initial delivery to the week beginning 7 March 2021, with additional shipments to follow shortly thereafter. The company will commence production of demonstration systems immediately upon receipt of packaged chips. ..."
Market Update – Progress Report - 30/3/21
Management is pleased to inform its shareholders that the company has produced both individual chips, and multi-chip boards that operate and play outside of the cleanroom.
As described in our 6 October 2020 market update, the primary objective of this development phase was to advance the technology so that devices can operate outside the confines of the cleanroom in its intended real-world environment.
The package has proven to protect the MEMS from the environment (dust particles, humidity etc.) with minimal acoustic attenuation, while providing an industry standard electrical interface.
The current setup operates up to 4 chips in parallel demonstrating the scalability of the technology.
Older versions of the MEMS chip were utilized for the first batches of packaged chips, as the iterative development process required large number of chips to be damaged during the packaging development and optimization process.
Once the packaging process is finalised, the latest generation of MEMS chips will then be packaged, and management will use these chips with the intention of being able to demonstrate the technology to its full extent.
Despite using the older generations of packaged MEMS chips the yield was sufficient to assemble several evaluation boards proving the chips, algorithms, software and electronics are working as expected.The company is in advanced stages of development of a stand-alone evaluation board that is capable of driving between 1 and 80 chips. This platform would be used to demonstrate sound performance, control algorithms, directivity manipulation and other advanced features of the technology.
Achievement of this milestone required overcoming rather extensive challenges to properly package the device in a manner that ensures that functional dies, while in wafer form, are not rendered inoperable as a result of the package or packaging process.
Packaging of a MEMS device is not only application specific, but has significant differences that render much of the equipment, tools and techniques commonly used to package conventional integrated circuits (IC’s), unusable. For example conventional pick-and-place tools, techniques and fixtures cannot be used to package a MEMS device, in order to avoid damaging the delicate surface features, the dies can only be handled from its sides, Another example is the inapplicability of many conventional adhesive materials and its application techniques when attaching the die or the lid to the substrate, as superfluous disbursement or unwarranted stress introduced by the adhesives, often leads to interference and failure of the devices micromechanical features.
This among other reasons is why most chip packaging houses do not package MEMS, and those that do, inherently require a substantial “learning curve” and multiple development iterations.
Management is all the more gratified that it was able to achieve this critical milestone while being severely encumbered by the COVID-19 pandemic. Limitations and restrictions associated with the pandemic prohibited the hands-on interaction, inspection and guidance typically required for such activities. Not only did these circumstances extend timelines but it also necessitated extra iterations to achieve the desired objectives, which is why older generations of MEMS dies were preferred during development and stabilization of the packaging process. Nonetheless despite all these limitations the demonstration systems work as intended, and will continually improve in the coming weeks as the packaging process is optimized and we begin to introduce newer generations of MEMS dies into the chip packaging process. ..."
27/4/21 Q1 Update Announcement
"... Achievement of this milestone continues to extend well beyond our originally scheduled plans as the company contends with widespread disruptions throughout the global semiconductor supply chain. Business and financial media extensively detail the impact global shortages have had on everything from electronics to medical devices to automobiles and networking and communications devices and equipment.
While the impact on our MEMS and ASIC wafer production has so far been manageable, the adverse effect on the packaging of our chips has been dramatic. As has been well documented the Company together with a world leading specialty chip packaging company, has spent over 5 years developing and perfecting an automated packaging process for our chips. Unfortunately, unprecedented production demands on our partner have so far prevented us from utilizing this packaging line.
While the Company has plans in place to meet future mass production demands, our short-term options to augment packaging capacity were extremely limited. Extending packaging capacity isn’t as simple as adding another production line or adding another vendor, as beyond the fact that seemingly the entire supply chain including equipment vendors are already at full capacity, and that it can take many months to order, receive and bring new equipment online; but unlike traditional semiconductor chips, the packaging of a MEMS device such as ours necessitates very specific and unique requirements.
We are very proud (and grateful) that the only chip packaging vendor in Israel agreed to support the Company through this crisis in bringing forth an interim solution to our chip packaging needs. Bringing a solution to bear, in particular at an accelerated pace, presents significant challenges as the vendor needed to gain the relevant knowledge, experience, tooling, processes and procedures, of which many are exclusive to our chips (further details were provided in the March 30th 2021 Announcement).
Notwithstanding the vendors commitment and diligence, it takes a large number of iterations to get the process correct and stable, during which a large number of MEMS dies must be sacrificed. Until such time that the process is reasonably reliable, the MEMS chips used to develop the packaging process are of the prior generation which are acoustically inferior and undesirable for public demonstration of our technologies. The assessment at the time of this report is that we need one to two additional iterations before being able to authorize the packaging of our newer generation of chips, pushing our demonstration milestone to the latter part of this fiscal quarter.
This announcement has been authorized for release to ASX by Fred Bart, Chairman. ..."
So that is where we are at. Fred says we need "one to two" additional iterations to ensure the process is acceptable before using good dies to make demo chips. How many is "one to two"? How long will this take? How long is a piece of string? If you have to second guess or doubt the answers you get given that is an open question. Fred Bart's answer is thus:
"...The assessment at the time of this report is that we need one to two additional iterations before being able to authorize the packaging of our newer generation of chips, pushing our demonstration milestone to the latter part of this fiscal quarter. ..."
Which fiscal quarter does he mean? The statement was made on 27/4/21, so that pushes it out as far as the end of June. But it could just get done by the AGM at the end of May, which I am sure would be a target if it proves at all possible.
I'm not booking a flight to Oz yet however.
(20min delay)